Zilog Z08470 - Manual (Page 29)

UM008007-0715 Interrupt Response
Z80 CPU
User Manual
17
Interrupt Response
An interrupt allows peripheral devices to suspend CPU operation and force the CPU to
start a peripheral service routine. This service routine usually involves the exchange of
data, status, or control information between the CPU and the peripheral. When the service
routine is completed, the CPU returns to the operation from which it was interrupted.
Interrupt Enable/Disable
The Z80 CPU contains two interrupt inputs: a software maskable interrupt (INT) and a
nonmaskable interrupt (NMI). The nonmaskable interrupt cannot be disabled by the pro-
grammer and is accepted when a peripheral device requests it. This interrupt is generally
reserved for important functions that can be enabled or disabled selectively by the pro-
grammer. This routine allows the programmer to disable the interrupt during periods when
the program contains timing constraints that wont allow interrupt. In the Z80 CPU, there is
an interrupt enable flip-flop (IFF) that is set or reset by the programmer using the Enable
Interrupt (EI) and Disable Interrupt (DI) instructions. When the IFF is reset, an interrupt
cannot be accepted by the CPU.
The two enable flip-flops are IFF1 and IFF2, as depicted in Figure 16.
Figure 15. Power-Down Release Cycle, #3 of 3
Figure 16. Interrupt Enable Flip-Flops
CLK
HALT
T1 T2 T3
M1
T4
INT
T1 T2 TWA TWA
IFF1 IFF2
Disables interrupts
from being accepted
Temporary storage
location for IFF1