Dec ss – Zilog Z08470 User Manual
Page 211
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UM008007-0715
Z80 Instruction Description
Z80 CPU
User Manual
199
DEC ss
Operation
ss ← ss – 1
Op Code
DEC
Operand
ss
Description
The contents of register pair ss (any of the register pairs BC, DE, HL, or SP) are decre-
mented. In the assembled object code, operand ss is specified as follows:
Condition Bits Affected
None.
Example
If register pair HL contains
1001h
, then upon the execution of an DEC HL instruction, HL
contains
1000h
.
Register
Pair
ss
BC
00
DE
01
HL
10
SP
11
M Cycles
T States
4 MHz E.T.
1
6
1.50
0
0
s
1
1
0
s
1
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