Zilog Z08470 - Manual (Page 117)

UM008007-0715 Z80 Instruction Description
Z80 CPU
User Manual
105
LD (nn), HL
Operation
(nn + 1) ← H, (nn) ← L
Op Code
LD
Operands
(nn), HL
Description
The contents of the low-order portion of register pair HL (Register L) are loaded to mem-
ory address (nn), and the contents of the high-order portion of HL (Register H) are loaded
to the next highest memory address (nn + 1). The first n operand after the op code is the
low-order byte of nn.
Condition Bits Affected
None.
Example
If register pair HL contains 483Ah , then upon the execution of an LD (B2291 – 1), HL
instruction, address B229h contains 3Ah and address B22Ah contains 48h .
M Cycles T States 4 MHz E.T.
5 16 (4, 3, 3, 3, 3) 4.00
0 0 0 1 0 0 1 0 22
n
n