Cpu response – Zilog Z08470 User Manual
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UM008007-0715
CPU Response
Z80 CPU
User Manual
19
CPU Response
The CPU always accepts a nonmaskable interrupt. When this nonmaskable interrupt is
accepted, the CPU ignores the next instruction that it fetches and instead performs a restart
at address
0066h
. The CPU functions as if it had recycled a restart instruction, but to a
location other than one of the eight software restart locations. A restart is merely a call to a
specific address in Page 0 of memory.
The CPU can be programmed to respond to the maskable interrupt in any one of three pos-
sible modes.
Mode 0
Mode 0 is similar to the 8080A interrupt response mode. With Mode 0, the interrupting
device can place any instruction on the data bus and the CPU executes it. Consequently,
the interrupting device provides the next instruction to be executed. Often this response is
a restart instruction because the interrupting device is required to supply only a single-byte
instruction. Alternatively, any other instruction such as a 3-byte call to any location in
memory could be executed.
The number of clock cycles necessary to execute this instruction is two more than the nor-
mal number for the instruction. The addition of two clock cycles occurs because the CPU
automatically adds two wait states to an Interrupt response cycle to allow sufficient time to
implement an external daisy-chain for priority control.
the timing for an interrupt response. After the application of RESET, the CPU automati-
cally enters interrupt Mode 0.
Mode 1
When Mode 1 is selected by the programmer, the CPU responds to an interrupt by execut-
ing a restart at address
0038h
. As a result, the response is identical to that of a nonmask-
able interrupt except that the call location is
0038h
instead of
0066h
. The number of
cycles required to complete the restart instruction is two more than normal due to the two
added wait states.
Mode 2
Mode 2 is the most powerful interrupt response mode. With a single 8-bit byte from the
user, an indirect call can be made to any memory location.
Accept NMI
0
*
Maskable
→ Interrupt.
RETN Instruction
Execution
IFF2
*
IFF2
→ Indicates completion of
nonmaskable interrupt service routine.
Table 1. Interrupt Enable/Disable, Flip-Flops (Continued)
Action
IFF1
IFF2
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