Zilog Z08470 - Manual (Page 206)

Z80 Instruction Set UM008007-0715
194
Z80 CPU
User Manual
ADD IY, rr
Operation
IY ← IY + rr
Op Code
ADD
Operands
IY, rr
Description
The contents of register pair rr (any of register pairs BC, DE, IY, or SP) are added to the
contents of Index Register IY, and the result is stored in IY. In the assembled object code,
the rr operand is specified as follows:
Condition Bits Affected
S is not affected.
Z is not affected.
H is set if carry from bit 11; otherwise, it is reset.
P/V is not affected.
Register
Pair ss
BC
00
DE
01
IY
10
SP
11
M Cycles T States 4 MHz E.T.
4 15 (4, 4, 4, 3) 3.75
1 1 1 0 1 1 1 1 FD
0 0 r 0 1 0 r 1