Zilog Z08470 - Manual (Page 27)

UM008007-0715 Power-Down Acknowledge Cycle
Z80 CPU
User Manual
15
The HALT instruction is repeated during the memory cycle shown in Figure 11.
Power-Down Acknowledge Cycle
When the clock input to the Z80 CPU is stopped at either a High or Low level, the Z80
CPU stops its operation and maintains all registers and control signals. However, ICC2
(standby supply current) is guaranteed only when the system clock is stopped at a Low
level during T4 of the machine cycle following the execution of the HALT instruction.
The timing diagram for the power-down function (when implemented with the HALT
instruction) is shown in Figure 12.
Figure 11. HALT Exit
Figure 12. Power-Down Acknowledge
CLK
RD or
HALT
M1
NMI
M1
T2 T4 T1 T3 T4 T1 T2
Note:
CLK
HALT
M1
T3 T1 T2 T4 T3 T2 T4 T1