Zilog Z08470 User Manual
Page 247
UM008007-0715
Z80 Instruction Description
Z80 CPU
User Manual
235
r identifies registers B, C, D, E, H, L, or A.
Description
The contents of operand m are shifted right 1 bit position. The contents of bit 0 are copied
to the Carry flag, and bit 7 is reset. Bit 0 is the least-significant bit.
Condition Bits Affected
S is reset.
Z is set if result is 0; otherwise, it is reset.
H is reset.
P/V is set if parity is even; otherwise, it is reset.
N is reset.
C is data from bit 0 of source register.
Example
Register B contains the following data.
Upon the execution of an SRL B instruction, Register B and the Carry flag now contain:
Instruction
M Cycles
T States
4 MHz E.T.
SRL r
2
8 (4, 4)
2.00
SRL (HL)
4
15 (4, 4, 4, 3)
3.75
SRL (IX+d)
6
23 (4, 4, 3, 5, 4, 3)
5.75
SRL (lY+d)
6
23 (4, 4, 3, 5, 4, 3)
5.75
1
0
0
1
1
1
0
1
7
6
4
1
0
2
5
3
1
1
0
1
0
0
1
0
7
6
4
1
0
2
5
3
C
1