Zilog Z08470 - Manual (Page 79)

UM008007-0715 Sign Flag
Z80 CPU
User Manual
67
Sign Flag
The Sign Flag (S) stores the state of the most-significant bit of the Accumulator (bit 7).
When the Z80 CPU performs arithmetic operations on signed numbers, the binary twos-
complement notation is used to represent and process numeric information. A positive
number is identified by a 0 in Bit 7. A negative number is identified by a 1. The binary
equivalent of the magnitude of a positive number is stored in bits 0 to 6 for a total range of
from 0 to 127. A negative number is represented by the twos complement of the equiva-
lent positive number. The total range for negative numbers is from –1 to –128.
When inputting a byte from an I/O device to a register using an IN r, (C) instruction, the S
Flag indicates either positive (S = 0) or negative (S = 1) data.
Z80 Instruction Description
Execution time (E.T.) for each instruction is provided in microseconds for an assumed
4 MHz clock. Total machine cycles (M) are indicated with total clock periods, or T states.
Also indicated are the number of T states for each M cycle, as shown in the following
example.
This example indicates that the instruction consists of two machine cycles. The first cycle
contains 4 clock periods/T states). The second cycle contains 3 clock periods, for a total of
7 clock periods/T states. The instruction executes in 1.75 microseconds.
In the register format of each of the instructions that follow, the most-significant bit to the
left and the least-significant bit to the right.
M Cycles T States E.T.
2 7(4,3) 4 MHz 1.75