Zilog Z08470 - Manual (Page 23)

UM008007-0715 Bus Request/Acknowledge Cycle
Z80 CPU
User Manual
11
*In Figure 7, TW is an automatically-inserted WAIT state.
Bus Request/Acknowledge Cycle
Figure 8 shows the timing for a Bus Request/Acknowledge cycle. The BUSREQ signal is
sampled by the CPU with the rising edge of the most recent clock period of any machine
cycle. If the BUSREQ signal is active, the CPU sets its address, data, and tristate control
signals to the high-impedance state with the rising edge of the next clock pulse. At that
time, any external device can control the buses to transfer data between memory and I/O
devices. (This operation is generally known as Direct Memory Access [DMA] using cycle
stealing.) The maximum time for the CPU to respond to a bus request is the length of a
machine cycle and the external controller can maintain control of the bus for as many
clock cycles as is required. If long DMA cycles are used, and dynamic memories are used,
the external controller also performs the refresh function. This situation only occurs if
Figure 7. Input or Output Cycles
Out
TW*
Write
Cycle
Read
Cycle
Port Address
CLK
IORQ
RD
WAIT
WR
In D7–D0
A15 –A0
D7–D0
T1 T2 T3 T1
Note: