Zilog Z08470 - Manual (Page 18)

Architectural Overview UM008007-0715
6
Z80 CPU
User Manual
RD, and WR have entered their high-impedance states. The external circuitry can now
control these lines.
BUSREQ. Bus Request (input, active Low). Bus Request contains a higher priority than
NMI and is always recognized at the end of the current machine cycle. BUSREQ forces
the CPU address bus, data bus, and control signals MREQ, IORQ, RD, and WR to enter a
high-impedance state so that other devices can control these lines. BUSREQ is normally
wired OR and requires an external pull-up for these applications. Extended BUSREQ peri-
ods due to extensive DMA operations can prevent the CPU from properly refreshing
dynamic RAM.
D7–D0. Data Bus (input/output, active High, tristate). D7–D0 constitute an 8-bit bidirec-
tional data bus, used for data exchanges with memory and I/O.
HALT. HALT State (output, active Low). HALT indicates that the CPU has executed a
HALT instruction and is waiting for either a nonmaskable or a maskable interrupt (with
the mask enabled) before operation can resume. During HALT, the CPU executes NOPs to
maintain memory refreshes.
INT. Interrupt Request (input, active Low). An Interrupt Request is generated by I/O
devices. The CPU honors a request at the end of the current instruction if the internal soft-
ware-controlled interrupt enable flip-flop (IFF) is enabled. INT is normally wired-OR and
requires an external pull-up for these applications.
IORQ. Input/Output Request (output, active Low, tristate). IORQ indicates that the lower
half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ
is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate
that an interrupt response vector can be placed on the data bus.
M1. Machine Cycle One (output, active Low). M1, together with MREQ, indicates that the
current machine cycle is the op code fetch cycle of an instruction execution. M1, when
operating together with IORQ, indicates an interrupt acknowledge cycle.
MREQ. Memory Request (output, active Low, tristate). MREQ indicates that the address
bus holds a valid address for a memory read or a memory write operation.
NMI. Nonmaskable Interrupt (input, negative edge-triggered). NMI contains a higher pri-
ority than INT. NMI is always recognized at the end of the current instruction, indepen-
dent of the status of the interrupt enable flip-flop, and automatically forces the CPU to
restart at location
0066h .
RD. Read (output, active Low, tristate). RD indicates that the CPU wants to read data from
memory or an I/O device. The addressed I/O device or memory should use this signal to
gate data onto the CPU data bus.
RESET. Reset (input, active Low). RESET initializes the CPU as follows: it resets the
interrupt enable flip-flop, clears the Program Counter and registers I and R, and sets the
interrupt status to Mode 0. During reset time, the address and data bus enter a high-imped-
ance state, and all control output signals enter an inactive state. RESET must be active for
a minimum of three full clock cycles before a reset operation is complete.