Zilog Z08470 - Manual (Page 54)

Z80 CPU Instructions UM008007-0715
42
Z80 CPU
User Manual
In this figure, note that the low-order portion of the address is always the first operand.
The load immediate instructions for the general-purpose 8-bit registers are two-byte
instructions. The instruction for loading Register H with the value
36h is written as:
LD H, 36h
The instruction sequence for this value in memory is shown in Figure 34.
Loading a memory location using indexed addressing for the destination and immediate
addressing for the source requires four bytes. For example:
LD (IX–15), 21h
The instruction sequence for this value in memory is shown in Figure 35.
Figure 33. Example of a 3-Byte Load Extended Instruction Sequence
Figure 34. Example of a 2-Byte Load Immediate Instruction Sequence
Figure 35. Example of a 4-Byte Load Indexed/Immediate Instruction Sequence
Op Code
Address A
A+1
A+2
3A
32
6F
low-order Address
high-order Address
Op Code Address A
A+1 Operand
26
36
Op Code
One or Two Bytes
Address A
A+1
A+2
A+3
DD
36
F1
21
Displacement (–15 in Signed
Two’s Complement
Operand to Load