Zilog Z08470 - Manual (Page 93)

UM008007-0715 Z80 Instruction Description
Z80 CPU
User Manual
81
LD (IY+d), r
Operation
(lY+d) ← r
Op Code
LD
Operands
(lY+d), r
Description
The contents of resister r are loaded to the memory address specified by the sum of the
contents of Index Register IY and d, a two’s-complement displacement integer. The r sym-
bol is specified according to the following table.
Condition Bits Affected
None.
Register r
A 111
B 000
C 001
D 010
E 011
H 100
L 101
M Cycles T States 4 MHz E.T.
5 19 (4, 4, 3, 5, 3) 4.75
d
1 1 1 0 1 1 1 1 FD
0 1 1 r 1 0