Zilog Z08470 - Manual (Page 325)

UM008007-0715 Z80 Instruction Description
Z80 CPU
User Manual
313
If B = 0:
Condition Bits Affected
S is unknown.
Z is set.
H is unknown.
P/V is unknown.
N is set.
C is not affected.
Example
Register C contains 07h , Register B contains 03h , the HL register pair contains 1000h ,
and memory locations contain the following data.
Upon the execution of an OTDR instruction, the HL register pair contain 0FFDh , Register
B contains a 0, and a group of bytes is written to the peripheral device mapped to I/O port
address
07h in the following sequence:
M Cycles T States 4 MHz E.T.
4 16 (4, 5, 3, 4) 4.00
0FFEh 51h
0FFFh A9h
1000h 03h
03h
A9h
51h