Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 197)

Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66E) 197
8.4.6 Interrupt Register 2
The CPCI CPLD, IPMI Controller, RTC, temperature sensor and abort switch interrupts are OR'd
together. This register may be read by the system software to determine which device
originated the interrupt.
Table 8-15 Interrupt Register 2, 0xF200_0005
Bit Field Operation Reset
7 RSVD R 0
6 RSVD R 0
5 RSVD R 0
4 CPCI_PLD_INT R 0
3 IPMI_INT R 0
2 RTC_INT R 0
1 TEMP_INT R 0
0 ABORT R 0
Table 8-16 Interrupt Register 2 Field Definition
RSVD Reserved
CPCI_PLD_INT Interrupt from CPCI Control CPLD
1 CPCI CPLD interrupt is asserted.
0 CPCI CPLD interrupt is not asserted.
IPMI_INT IPMI Controller Interrupt
1 IPMI interrupt is asserted.
0 IPMI interrupt is not asserted.
RTC_INT RTC Interrupt
1 RTC interrupt is asserted.
0 RTC interrupt is not asserted.