Document Outline

• Chapter1 General Description
  • Figure1.1 Typical LSI53C895A System Application
  • Figure1.2 Typical LSI53C895A Board Application
  • 1.1 New Features in the LSI53C895A
  • 1.2 Benefits of Ultra2 SCSI
  • 1.3 Benefits of LVDlink
  • 1.4 TolerANT® Technology
  • 1.5 LSI53C895A Benefits Summary
    • 1.5.1 SCSI Performance
    • 1.5.2 PCI Performance
    • 1.5.3 Integration
    • 1.5.4 Ease of Use
    • 1.5.5 Flexibility
    • 1.5.6 Reliability
    • 1.5.7 Testability
• Chapter2 Functional Description
  • Figure2.1 LSI53C895A Block Diagram
  • 2.1 PCI Functional Description
    • 2.1.1 PCI Addressing
      • 2.1.1.1 Configuration Space
      • 2.1.1.2 I/O Space
      • 2.1.1.3 Memory Space
    • 2.1.2 PCI Bus Commands and Functions Supported
      • Table 2.1 PCI Bus Commands and Encoding Types for the LSI53C895A
      • 2.1.2.1 Interrupt Acknowledge Command
      • 2.1.2.2 Special Cycle Command
      • 2.1.2.3 I/O Read Command
      • 2.1.2.4 I/O Write Command
      • 2.1.2.5 Reserved Command
      • 2.1.2.6 Memory Read Command
      • 2.1.2.7 Memory Write Command
      • 2.1.2.8 Configuration Read Command
      • 2.1.2.9 Configuration Write Command
      • 2.1.2.10 Memory Read Multiple Command
      • 2.1.2.11 Dual Address Cycle (DAC) Command
      • 2.1.2.12 Memory Read Line Command
      • 2.1.2.13 Memory Write and Invalidate Command
    • 2.1.3 PCI Cache Mode
      • 2.1.3.1 Enabling Cache Mode
      • 2.1.3.2 Issuing Cache Commands
      • 2.1.3.3 Memory Read Caching
      • 2.1.3.4 Memory Write Caching
        • Table 2.2 PCI Cache Mode Alignment
      • 2.1.3.5 Examples:
      • 2.1.3.6 Memory-to-Memory Moves
  • 2.2 SCSI Functional Description
    • 2.2.1 SCRIPTS Processor
      • 2.2.1.1 Phase Mismatch Handling in SCRIPTS
    • 2.2.2 Internal SCRIPTS RAM
    • 2.2.3 64-Bit Addressing in SCRIPTS
    • 2.2.4 Hardware Control of SCSI Activity LED
    • 2.2.5 Designing an Ultra2 SCSI System
      • 2.2.5.1 Using the SCSI Clock Quadrupler
    • 2.2.6 Prefetching SCRIPTS Instructions
    • 2.2.7 Opcode Fetch Burst Capability
    • 2.2.8 Load and Store Instructions
    • 2.2.9 JTAG Boundary Scan Testing
    • 2.2.10 SCSI Loopback Mode
    • 2.2.11 Parity Options
      • Table 2.3 Bits Used for Parity Control and Generation
      • Table 2.4 SCSI Parity Control
      • Table 2.5 SCSI Parity Errors and Interrupts
      • Figure2.2 Parity Checking/Generation
    • 2.2.12 DMA FIFO
      • Figure2.3 DMA FIFO Sections
      • 2.2.12.1 Data Paths
        • Figure2.4 LSI53C895A Host Interface SCSI Data Paths
    • 2.2.13 SCSI Bus Interface
      • 2.2.13.1 LVDlink Technology
      • 2.2.13.2 HVD Mode
        • Table 2.6 HVD Signals
        • Figure2.5 8-Bit HVD Wiring Diagram for Ultra2 SCSI
      • 2.2.13.3 SCSI Termination
        • Figure2.6 Regulated Termination for Ultra2 SCSI
    • 2.2.14 Select/Reselect During Selection/Reselection
    • 2.2.15 Synchronous Operation
      • 2.2.15.1 Determining the Data Transfer Rate
        • Figure2.7 Determining the Synchronous Transfer Rate
      • 2.2.15.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0])
      • 2.2.15.3 SCSI Control Three (SCNTL3) Register, Bits [2:0] (CCF[2:0])
      • 2.2.15.4 SCSI Transfer (SXFER) Register, Bits [7:5] (TP[2:0])
      • 2.2.15.5 Ultra2 SCSI Synchronous Data Transfers
    • 2.2.16 Interrupt Handling
      • 2.2.16.1 Polling and Hardware Interrupts
      • 2.2.16.2 Registers
      • 2.2.16.3 Fatal vs. Nonfatal Interrupts
      • 2.2.16.4 Masking
      • 2.2.16.5 Stacked Interrupts
      • 2.2.16.6 Halting in an Orderly Fashion
      • 2.2.16.7 Sample Interrupt Service Routine
    • 2.2.17 Interrupt Routing
    • 2.2.18 Chained Block Moves
      • Figure2.8 Block Move and Chained Block Move Instructions
      • 2.2.18.1 Wide SCSI Send Bit
      • 2.2.18.2 Wide SCSI Receive Bit
      • 2.2.18.3 SWIDE Register
      • 2.2.18.4 SODL Register
      • 2.2.18.5 Chained Block Move SCRIPTS Instruction
  • 2.3 Parallel ROM Interface
    • Table 2.7 Parallel ROM Support
  • 2.4 Serial EEPROM Interface
    • 2.4.1 Default Download Mode
      • Table 2.8 Mode A Serial EEPROM Data Format
    • 2.4.2 No Download Mode
  • 2.5 Alternative SSVID/SSID Loading Mechanism
  • 2.6 Power Management
    • Table 2.9 Power States
    • 2.6.1 Power State D0
    • 2.6.2 Power State D1
    • 2.6.3 Power State D2
    • 2.6.4 Power State D3
• Chapter3 Signal Descriptions
  • 3.1 LSI53C895A Functional Signal Grouping
    • Figure3.1 LSI53C895A Functional Signal Grouping
  • 3.2 Signal Descriptions
    • 3.2.1 Internal Pull-ups on LSI53C895A Signals
      • Table 3.1 LSI53C895A Internal Pull-ups
  • 3.3 PCI Bus Interface Signals
    • 3.3.1 System Signals
      • Table 3.2 System Signals
    • 3.3.2 Address and Data Signals
      • Table 3.3 Address and Data Signals
    • 3.3.3 Interface Control Signals
      • Table 3.4 Interface Control Signals
    • 3.3.4 Arbitration Signals
      • Table 3.5 Arbitration Signals
    • 3.3.5 Error Reporting Signals
      • Table 3.6 Error Reporting Signals
    • 3.3.6 Interrupt Signals
      • Table 3.7 Interrupt Signals
    • 3.3.7 SCSI GPIO Signals
      • Table 3.8 SCSI GPIO Signals
  • 3.4 SCSI Bus Interface Signals
    • 3.4.1 SCSI Bus Interface Signal
      • Table 3.9 SCSI Bus Interface Signal
    • 3.4.2 SCSI Signals
      • Table 3.10 SCSI Signals
    • 3.4.3 SCSI Control Signals
      • Table 3.11 SCSI Control Signals
  • 3.5 Flash ROM and Memory Interface Signals
    • Table 3.12 Flash ROM and Memory Interface Signals
  • 3.6 Test Interface Signals
    • Table 3.13 Test Interface Signals
  • 3.7 Power and Ground Signals
    • Table 3.14 Power and Ground Signals
  • 3.8 MAD Bus Programming
    • Table 3.15 Decode of MAD Pins
• Chapter4 Registers
  • 4.1 PCI Configuration Registers
    • Table 4.1 PCI Configuration Register Map
  • 4.2 SCSI Registers
    • Table 4.2 SCSI Register Address Map
    • Table 4.3 Examples of Synchronous Transfer Periods and Rates for SCSI-1
    • Table 4.4 Example Transfer Periods and Rates for Fast SCSI-2, Ultra, and Ultra2
    • Table 4.5 Maximum Synchronous Offset
    • Table 4.6 SCSI Synchronous Data FIFO Word Count
  • 4.3 64-Bit SCRIPTS Selectors
  • 4.4 Phase Mismatch Jump Registers
• Chapter5 SCSI SCRIPTS Instruction Set
  • 5.1 Low Level Register Interface Mode
  • 5.2 High Level SCSI SCRIPTS Mode
    • Table 5.1 SCRIPTS Instructions
    • 5.2.1 Sample Operation
      • Figure5.1 SCRIPTS Overview
  • 5.3 Block Move Instruction
    • 5.3.1 First Dword
      • Table 5.2 SCSI Information Transfer Phase
    • 5.3.2 Second Dword
  • 5.4 I/O Instruction
    • 5.4.1 First Dword
    • 5.4.2 Second Dword
  • 5.5 Read/Write Instructions
    • 5.5.1 First Dword
    • 5.5.2 Second Dword
    • 5.5.3 Read-Modify-Write Cycles
    • 5.5.4 Move To/From SFBR Cycles
      • Table 5.3 Read/Write Instructions
  • 5.6 Transfer Control Instructions
    • 5.6.1 First Dword
      • Table 5.4 Transfer Control Instructions
      • Table 5.5 SCSI Phase Comparisons
    • 5.6.2 Second Dword
  • 5.7 Memory Move Instructions
    • 5.7.1 First Dword
    • 5.7.2 Read/Write System Memory from SCRIPTS
    • 5.7.3 Second Dword
    • 5.7.4 Third Dword
  • 5.8 Load and Store Instructions
    • 5.8.1 First Dword
    • 5.8.2 Second Dword
• Chapter6 Electrical Specifications
  • 6.1 DC Characteristics
    • Table 6.1 Absolute Maximum Stress Ratings
    • Table 6.2 Operating Conditions
    • Table 6.3 LVD Driver SCSI Signals—SD[15:0]+, SDP[1:0]/, SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SIO/...
    • Figure6.1 LVD Driver
    • Table 6.4 LVD Receiver SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SI...
    • Figure6.2 LVD Receiver
    • Table 6.5 DIFFSENS SCSI Signal
    • Table 6.6 Input Capacitance
    • Table 6.7 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/
    • Table 6.8 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO[2:8]
    • Table 6.9 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/...
    • Table 6.10 Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST, TMS, TRST/
    • Table 6.11 Output Signal—TDO
    • Table 6.12 Output Signals—ALT_IRQ/, IRQ/, MAC/_TESTOUT, REQ/
    • Table 6.13 Output Signal—SERR/
  • 6.2 TolerANT Technology Electrical Characteristics
    • Table 6.14 TolerANT Technology Electrical Characteristics for SE SCSI Signals
    • Figure6.3 Rise and Fall Time Test Condition
    • Figure6.4 SCSI Input Filtering
    • Figure6.5 Hysteresis of SCSI Receivers
    • Figure6.6 Input Current as a Function of Input Voltage
    • Figure6.7 Output Current as a Function of Output Voltage
  • 6.3 AC Characteristics
    • Table 6.15 External Clock
    • Figure6.8 External Clock
    • Table 6.16 Reset Input
    • Figure6.9 Reset Input
    • Table 6.17 Interrupt Output
    • Figure6.10 Interrupt Output
  • 6.4 PCI and External Memory Interface Timing Diagrams
    • 6.4.1 Target Timing
      • Table 6.18 PCI Configuration Register Read
      • Figure6.11 PCI Configuration Register Read
      • Table 6.19 PCI Configuration Register Write
      • Figure6.12 PCI Configuration Register Write
      • Table 6.20 32-Bit Operating Register/SCRIPTS RAM Read
      • Figure6.13 32-Bit Operating Register/SCRIPTS RAM Read
      • Table 6.21 64-Bit Address Operating Register/SCRIPTS RAM Read
      • Figure6.14 64-Bit Address Operating Register/SCRIPTS RAM Read
      • Table 6.22 32-Bit Operating Register/SCRIPTS RAM Write
      • Figure6.15 32-Bit Operating Register/SCRIPTS RAM Write
      • Table 6.23 64-Bit Address Operating Register/SCRIPTS RAM Write
      • Figure6.16 64-Bit Address Operating Register/SCRIPTS RAM Write
    • 6.4.2 Initiator Timing
      • Table 6.24 Nonburst Opcode Fetch, 32-Bit Address and Data
      • Figure6.17 Nonburst Opcode Fetch, 32-Bit Address and Data
      • Table 6.25 Burst Opcode Fetch, 32-Bit Address and Data
      • Figure6.18 Burst Opcode Fetch, 32-Bit Address and Data
      • Table 6.26 Back to Back Read, 32-Bit Address and Data
      • Figure6.19 Back to Back Read, 32-Bit Address and Data
      • Table 6.27 Back to Back Write, 32-Bit Address and Data
      • Figure6.20 Back to Back Write, 32-Bit Address and Data
      • Table 6.28 Burst Read, 32-Bit Address and Data
      • Figure6.21 Burst Read, 32-Bit Address and Data
      • Table 6.29 Burst Read, 64-Bit Address and Data
      • Figure6.22 Burst Read, 64-Bit Address and Data
      • Table 6.30 Burst Write, 32-Bit Address and Data
      • Figure6.23 Burst Write, 32-Bit Address and Data
      • Table 6.31 Burst Write, 64-Bit Address and 32-Bit Data
      • Figure6.24 Burst Write, 64-Bit Address and 32-Bit Data
    • 6.4.3 External Memory Timing
      • Table 6.32 External Memory Read
      • Figure6.25 External Memory Read
      • Table 6.33 External Memory Write
      • Figure6.26 External Memory Write
      • Table 6.34 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle
      • Figure6.27 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle
      • Table 6.35 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle
      • Figure6.28 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle
      • Figure6.29 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Read Cycle
      • Figure6.30 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Write Cycle
      • Table 6.36 Slow Memory (£ 128 Kbytes) Read Cycle
      • Figure6.31 Slow Memory (£ 128 Kbytes) Read Cycle
      • Table 6.37 Slow Memory (£ 128 Kbytes) Write Cycle
      • Figure6.32 Slow Memory (£ 128 Kbytes) Write Cycle
      • Table 6.38 £ 64 Kbytes ROM Read Cycle
      • Figure6.33 £ 64 Kbytes ROM Read Cycle
      • Table 6.39 £ 64 Kbyte ROM Write Cycle
      • Figure6.34 £ 64 Kbyte ROM Write Cycle
  • 6.5 SCSI Timing Diagrams
    • Table 6.40 Initiator Asynchronous Send
    • Figure6.35 Initiator Asynchronous Send
    • Table 6.41 Initiator Asynchronous Receive
    • Figure6.36 Initiator Asynchronous Receive
    • Table 6.42 Target Asynchronous Send
    • Figure6.37 Target Asynchronous Send
    • Table 6.43 Target Asynchronous Receive
    • Figure6.38 Target Asynchronous Receive
    • Table 6.44 SCSI-1 Transfers (SE 5.0 Mbytes)
    • Table 6.45 SCSI-1 Transfers (Differential 4.17 Mbytes)
    • Table 6.46 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...
    • Table 6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...
    • Table 6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers...
    • Table 6.49 Ultra SCSI High Voltage Differential Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 M...
    • Table 6.50 Ultra2 SCSI Transfers 40.0 Mbytes (8-Bit Transfers) or 80.0 Mbytes (16-Bit Transfers) ...
    • Figure6.39 Initiator and Target Synchronous Transfer
  • 6.6 Package Diagrams
    • Figure6.40 LSI53C895A 272-Pin BGA Top View
    • Table 6.51 272 BGA Pin List by Location
    • Table 6.52 BGA Pin List Alphabetically
    • Figure6.41 LSI53C895A 208-Pin Plastic Quad Flat Pack
    • Table 6.53 Signal Names vs. Pin Number: 208-Pin Plastic Quad Flat Pack
    • 6.6.1 LSI53C895A vs. LSI53C895 Pin/Ball Differences
      • Table 6.54 LSI53C895A vs. LSI53C895 Pin/Ball Differences
      • Figure6.42 LSI53C895A 208 PQFP Mechanical Drawing (Sheet 1 of 2)
      • Figure6.43 LSI53C895A 272 PBGA Mechanical Drawing
• AppendixA Register Summary
  • TableA.1 LSI53C895A PCI Register Map
  • TableA.2 LSI53C895A SCSI Register Map
• AppendixB External Memory Interface Diagram Examples
  • FigureB.1 16 Kbyte Interface with 200 ns Memory
  • FigureB.2 64 Kbyte Interface with 150 ns Memory
  • FigureB.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 ns Memory
  • FigureB.4 512 Kbyte Interface with 150 ns Memory
• Index
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