Altera SerialLite II IP Core - Manual (Page 61)

Chapter 4: Functional Description 4–7
Clocks and Data Rates
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
SerialLite II Clocking Structure
Figure 4–6 through Figure 4–12 show the MegaCore function clock structures, which
vary based on the configuration parameters.
Figure 4–6. Full-Featured Clock Structure
Note to Figure 4–6 :
(1) Individual recovered clocks (one per channel).
slite2_top
XCVR
Word Aligner (&
Training Pattern
Detection),
[Link State
Machine]
TX Core
n-bit
n-bit
RX Core
n-bit
Atlantic
#n SLITE2
High
Speed
Links
#m SLITE2
High
Speed
Links
Atlantic
Atlantic
Atlantic
Regular
Priority
Priority
Regular
PComp_FIFO_0
Byte
serializer
Byte
serializer
PComp_FIFO_n-1
Byte
deserializer
Byte
deserializer
n-bit
rxrdp_clk
rxhpp_clk
txhpp_clk
txrdp_clk
rrefclk
rcvd_clk0
rcvd_clkn-1
trefclk
tx_coreclk
RREFCLK
mreset_n
Reset Sync
tx_coreclk
rcvd_clk_out[n-1:0] (1)
Freq Off
Removal
Freq Off
Removal
ATLFIFO
ATLFIFO
ATLFIFO
ATLFIFO
rrefclk
rrefclk
Training
Generator [Link
State Machine]
TXPLL
tx_coreclk
tx_coreclk
tx_coreclk
tx_coreclk