Altera SerialLite II IP Core - Manual (Page 65)

Chapter 4: Functional Description 4–11
Clocks and Data Rates
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Figure 4–10. Streaming Full-Featured Clock Structure
Note to Figure 4–10 :
(1) Individual recovered clocks (one per channel).
slite2_top
XCVR
n-bit
n-bit
n-bit
#n SLITE2
High
Speed
Links
#m SLITE2
High
Speed
Links
PComp_FIFO_0
Byte
serializer
Byte
serializer
PComp_FIFO_n-1
Byte
deserializer
Byte
deserializer
n-bit
rcvd_clk0
rcvd_clkn-1
tx_coreclock
RREFCLK
mreset_n
Reset Sync
tx_coreclock
rcvd_clk_out[n-1:0] (1)
Word Aligner (&
Training Pattern
Detection),
[Link State
Machine]
Training
Generator [Link
State Machine]
Atlantic
Regular
(tx_coreclock
domain)
Atlantic
Regular
(tx_coreclock
domain)
Freq Off
Removal
rrefclk
trefclk
TXPLL
tx_coreclock