Altera SerialLite II IP Core - Manual (Page 64)

4–10 Chapter 4: Functional Description
Clocks and Data Rates
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Figure 4–9. No Receiver FIFO Buffers No Frequency Offset Clock Structure
Note to Figure 4–9 :
(1) Individual recovered clocks (one per channel).
slite2_top
XCVR
TX Core
n-bit
n-bit
RX Core
n-bit
#n SLITE2
High
Speed
Links
#m SLITE2
High
Speed
Links
Atlantic
Atlantic
Priority
Regular
PComp_FIFO_0*
Byte
serializer
Byte
serializer
PComp_FIFO_n-1
Byte
deserializer
Byte
deserializer
n-bit
txhpp_clk
txrdp_clk
rcvd_clk0
rcvd_clkn-1
tx_coreclock
RREFCLK
mreset_n
Reset Sync
tx_coreclock
rcvd_clk_out[n-1:0]
ATLFIFO
ATLFIFO
rrefclk
Word Aligner (&
Training Pattern
Detection),
[Link State
Machine]
Training
Generator [Link
State Machine]
Atlantic
Regular
(rrefclk
domain)
Atlantic
Priority
(rrefclk
domain)
trefclk
TXPLL
tx_coreclock
tx_coreclock
(1)