Altera SerialLite II IP Core - Manual (Page 83)

Chapter 4: Functional Description 4–29
Signals
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Table 4–10 shows the troubleshooting signals. These signals do not necessarily need to
be connected to external logic. In general, they are for diagnostic purposes. Some
signals in
Table 4–10 are only available in certain configurations.
Table 4–10. Troubleshooting Signals (Part 1 of 2)
Signal Direction Clock Domain Description
stat_tc_rst_done Output tx_coreclock
Reset controller logic Done signal. When
high, the reset controller has completed the
ALTGXB reset sequence successfully.
err_rr_foffre_oflw (1) Output rrefclk
Indicates that frequency offset tolerance FIFO
buffer has overflowed. The link restarts.
stat_tc_foffre_empty (1) Output tx_coreclock
Indicates that frequency offset tolerance FIFO
buffer has underflowed. The link does not go
down. IDLE characters are inserted. This
does not have a negative impact on the core,
and is simply for diagnostic purposes.
stat_rr_ebprx (1) Output rrefclk
Indicates that an end of bad packet character
was received.
err_rr_bip8 (1) Output rrefclk
Indicates that a BIP-8 error was detected in
the received link management packet.
err_rr_crc (1) Output rrefclk
Indicates that a CRC error was detected in the
received segment/packet.
err_rr_fcrx_bne (1) Output rrefclk
Indicates that a flow control link management
packet was received, but flow control is not
enabled.
err_rr_roerx_bne (1) Output rrefclk
Indicates that a retry-on-error link
management packet was received, but Retry-
on-error parameter is not enabled.
err_rr_invalid_lmprx (1) Output rrefclk
Indicates that an invalid link management
packet was received.
err_rr_missing_start_dcw (1) Output rrefclk
Indicates that data byte(s) received, but a
start of data control word (DCW) is missing.
err_addr_mismatch (1) Output rrefclk
Indicates that the start and end address fields
do not match. Segments are marked with an
error. Possible packets are destined for an
invalid address.
err_rr_pol_rev_required (1) Output rrefclk
May indicate catastrophic error. Polarity on
the input ALTGXB lines is reversed; the
MegaCore function cannot operate.
If you see the signal for the first time, you
should manually reset the core. If the signal
triggers again after you reset, then it
confirms a catastrophic error.
err_rr_dskfifo_oflw (1) Output rrefclk
Indicates that deskew FIFO buffer has
overflowed. Link restarts.
stat_rr_dskw_done_bc (1) Output rrefclk
Indicates that a bad column was received
after successful deskew completion. Link is
restarted.