Altera SerialLite II IP Core - Manual (Page 94)

5–8 Chapter 5: Testbench
Simulation Flow
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench)
The simulation allows .vcd file generation if WAVEFORM is tick defined. All signals
are included in the dump file (dumpfile.vcd).
Testbench Time-Out
The testbench uses a maximum simulation time to guard against infinite loops or
stuck simulations. The default value of 500,000,000 picoseconds is sufficient for most
simulation runs. However, if more time is needed for a particularly long run, you can
increase the WATCHTIME value. For example, change the already defined
WATCHTIME inside the testbench main section to `define WATCHTIME 100,000,000
for Verilog HDL or for VHDL edit the <variation_name>_tb.vhd to change the constant
WATCHTIME: time: = 100000000 ns
;
In Verilog HDL, an alternative to increasing the WATCHTIME is to reset the watch timer
from time to time (for example, after each test case or even after each packet is sent) by
adding the following line, as needed, to the testbench main section:
reset_watchdog_timer;
Every time the reset_watchdog_timer task is called, the testbench time-out resets
with another WATCHTIME time.
Special Simulation Configuration Settings
The SerialLite II MegaCore function contains few settings that have a reduced value in
simulation:
# 20000 ns : tb progressing..
# AMON_DAT_DUT 5: received packet id=0 addr=0xd5 err=1, time: 21964 ns
# AMON_DAT_DUT 15: received packet id=0 addr=0x0f err=0, time: 22726 ns
# AMON_DAT_DUT 8: received packet id=0 addr=0x98 err=0, time: 25070 ns
# AMON_DAT_DUT 4: received packet id=0 addr=0xa4 err=1, time: 25263 ns
# AMON_DAT_DUT: Received ALL 5 packets, time: 25263 ns
# 25263 ns RUNNING TESTCASE_END #1: example_tb
# ***************************************************************
# $$$ End of testbench example_tb at : 25263 ns
# $$$ AUTHOR: unknown
# $$$ DATE: `DATE
# RUNNING ACTUAL_TC = 1 RUNNING EXPECTED_TC = 1
# RUNNING ACTUAL_ERR = 0,
# $$$ Exit status for testbench example_tb : TESTBENCH_PASSED
# ***************************************************************
# ** Note: Data structure takes 74588614 bytes of memory
# Process time 495.56 seconds
# $finish : example_tb.v(1070)
# Time: 25263352 ps Iteration: 0 Instance: /tb
Example 5–1. run_modelsim.log (Part 2 of 2)
Example 5–2.
# add the following tick define to the testbench to
# create a VCD
`define WAVEFORM
# add the following to the simulator command line to
# create a VCD dump file.
+define+WAVEFORM