Altera SerialLite II IP Core - Manual (Page 92)

5–6 Chapter 5: Testbench
Simulation Flow
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Running a Simulation
Altera provides a ModelSim simulation script that allows you to run a simulation
based on the simulation configuration you have chosen. To run the simulation while
in the ModelSim Tcl environment, first ensure that you have set the Quartus II project
directory to be the working directory.
1. Run ModelSim (vsim) to bring up the user interface.
2. Execute the simulation run, by typing the appropriate command:
do <variation name>_run_modelsim.tcl (Verilog HDL)
or
do <variation_name>_run_modelsim_vhdl.tcl (VHDL)
The testbench creates the run_modelsim.log file as an output file.
1 If you select Arria V or Stratix V as the target device family, you are required to add a
list of the Custom PHY IP core simulation files into the command line Tcl file. For
more information about the simulation support, refer to
“MegaCore Configuration for
Arria V, Cyclone V, and Stratix V Devices” on page 4–19 .
Simulation Pass and Fail Conditions
The meaning of pass or fail can vary based on intent, so this section clarifies what it
means when a simulation run ends and failure is reported.
The execution of a simulation run consists of the following components:
■ Create data to be transported through the link
■ Verify that the data arrived with or without errors
■ Verify that the various protocols were honored in the delivery of the data
■ Confirm that the state of the link is consistent
The testbench concludes by checking that all of the packets have been received. In
addition, it checks that the Atlantic packet receivers (amon modules) have not detected
any errors in the received packets.
If no errors are detected, and all packets are received, the testbench issues a message
stating that the simulation was successful.
If errors were detected, a message states that the testbench has failed. If not all packets
have been detected, the testbench eventually times out (time limit set by
WATCHTIME), which causes an error and the testbench to fail.
In summary, the testbench checks the following:
■ Were all expected stimulus generated?
■ Did all expected packets arrive and was the data error-free?
■ If errors occurred on the data, did the SerialLite II logic detect the errors?
■ Were there any protocol errors?
■ Is there any evidence of the simulation running too long out of control?