Altera SerialLite II IP Core - Manual (Page 63)

Chapter 4: Functional Description 4–9
Clocks and Data Rates
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Figure 4–8. Full-Featured No Frequency Offset Clock Structure
Note to Figure 4–8 :
(1) Individual recovered clock (one per channel).
slite2_top
XCVR
TX Core
n-bit
n-bit
RX Core
n-bit
Atlantic
#n SLITE2
High
Speed
Links
#m SLITE2
High
Speed
Links
Atlantic
Atlantic
Atlantic
Regular
Priority
Priority
Regular
PComp_FIFO_0
Byte
Serializer
Byte
Serializer
PComp_FIFO_n-1
Byte
Deserializer
Byte
Deserializer
n-bit
rxrdp_clk
rxhpp_clk
txhpp_clk
txrdp_clk
rcvd_clk0
rcvd_clkn-1
tx_coreclock
RREFCLK
mreset_n
Reset Sync
tx_coreclock
rcvd_clk_out[n-1:0] (1)
Atlantic FIFO Buffer
Atlantic FIFO Buffer
Atlantic
FIFO
Buffer
Atlantic
FIFO
Buffer
rrefclk
rrefclk
rrefclk
Word Aligner (&
Training Pattern
Detection),
[Link State
Machine]
Training
Generator [Link
State Machine]
trefclk
TXPLL
tx_coreclock
tx_coreclock
rrefclk