Altera External Memory PHY Interface - Manual (Page 19)

Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–3
QDR II+/QDR II SRAM Calibration Process
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
During the QDR II+/QDR II SRAM calibration, the sequencer first writes all 0s to
address space 3 in the external memory, followed by all 1s to address space 5. It then
loads the scan chain for the first time, to program the first setting for
resync_clk_1x
.
The sequencer then starts reading 0s from address space 3 several times, followed by a
single read from address space 5 and starts the latency counter. If a pattern of all 0s
followed by all 1s is read before the latency counter reaches its time-out value (31
clock cycles), the latency value for that memory device is stored.
If all 0s followed by all 1s is not found when reading back from memory and the
latency count has reached the time-out value, the sequencer loads the scan chains a
second time to invert the resync_clk_1x signal. The sequencer then starts reading
from address space 3 several times, followed by a single read from address space 5 as
before and starts the latency counter again. If all 0s followed by all 1s are read back
from memory, the latency value for that memory device is stored.
1 The training pattern must be read back correctly on this second iteration (if it was not
already read correctly on the first iteration). If it is not read back correctly, it indicates
an underlying problem in the system.
The previous process is repeated until all memory devices are tested and a latency
value obtained for each device.
The latency values found for the different devices are compared with each other. If
necessary, they are aligned to the worst case latency (or to the user-requested
deterministic latency value if this option is used), which done by adjusting address
pointers in order to add latency to some of the read datapath RAMs inside the
ALTMEMPHY megafunction until the latency associated with all of the memory
devices is aligned to the worst case latency measured.
1 You cannot have a latency difference of more than two PHY clock cycles between all
the QDR II+/QDR II SRAM devices in non-deterministic latency mode.
When calibration has finished, the sequencer hands over control to the driver/user
logic, and generates the p_rdata_out_valid flag to indicate when read data is
valid. The sequencer also outputs the following signals upon completion of
calibration:
■ p_ready —Indicates completion of the calibration process (but does not mean
calibration was successful). This signal is renamed as the ctl_usr_mode_rdy
signal at the ALTMEMPHY top-level file.
■ p_calibration_successful —Indicates calibration was successfully
completed. This port is renamed resynchronisation_successful port at the
ALTMEMPHY top-level file.
■ p_user_defined_latency_ok —Indicates that the read latency requested by
the user was achievable, when using deterministic latency. This port is not
instantiated at the top-level of the file. Currently this signal exists at the
sequencer_wrapper
file level only.
■ p_detectedlatency —Specifies the read latency achieved in phy_clk clock
cycles. This port is renamed ctl_rlat port at the ALTMEMPHY top-level file.