Altera External Memory PHY Interface - Manual (Page 24)

3–8 Chapter 3: Functional Description—ALTMEMPHY (nonAFI)
Initialization Timing
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide © January 2010 Altera Corporation
The following sequence corresponds with the numbered items in Figure 3–5 on
page 3–7 .
1. The clock enable signal (CKE) is asserted 200 µs after coming out of reset.
2. The controller then waits 400 ns and then issues the first PCH command by setting
the precharge pin, the address bit a[10] or a[8] high. The 400 ns is calculated by
taking the number of clock cycles calculated by the wizard for the 200 µs delay and
dividing this by 500. If a small initialization time is selected for simulation
purposes, this delay is always at least 1 clock cycle.
3. Two ELMR commands are issued to load extend mode registers 2 and 3 with
zeros.
4. An ELMR command is issued to extend mode register 1 to enable the internal DLL
in the memory devices.
5. An LMR command is issued to set the operating parameters of the memory such
as CAS latency and burst length. This LMR command is also used to reset the
internal memory device DLL.
6. A further PCH command places all the banks in their idle state.
7. Two ARF commands must follow the PCH command.
8. A final LMR command is issued to program the operating parameters without
resetting the DLL.
9. 200 clock cycles after step 5 , two ELMR commands are issued to set the memory
device off-chip driver (OCD) impedance to the default setting.
After issuing the final ELMR command, the memory controller hands over control of
the memory to the ALTMEMPHY megafunction to allow it to carry out its calibration
process.
When ALTMEMPHY megafunction has finished calibrating, the memory controller
asserts the local_init_done signal, which shows that it has initialized the memory
devices.