Altera External Memory PHY Interface - Manual (Page 75)

Chapter 4: Support for Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices 4–7
DDR2/DDR SDRAM
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
DLL
A DLL instance is included in the generated ALTMEMPHY variation. When using the
DQS to capture the DQ read data, the DLL center-aligns the DQS strobe to the DQ
data. The DLL settings depend on the interface clock frequency.
f
For more information, refer to the External Memory Interfaces chapter in the device
handbook for your target device family.
Reset Management
The reset management block is responsible for the following:
■ Provides appropriately timed resets to the ALTMEMPHY megafunction datapaths
and functional modules
■ Performs the reset sequencing required for different clock domains
■ Provides reset management of PLL and PLL reconfiguration functions
■ Manages any circuit-specific reset sequencing
Each reset is an asynchronous assert and synchronous de-assert on the appropriate
clock domain. The reset management design uses a standard two-register
synchronizer to avoid metastability. A unique reset metastability protection circuit for
the clock divider circuit is required because the phy_clk domain reset metastability
protection flipflops have fan-in from the soft_reset_n input, and so these registers
cannot be used.
Figure 4–3 shows the ALTMEMPHY reset management block for Arria GX,
HardCopy II, Stratix II, and Stratix II GX devices. The pll_ref_clk signal goes
directly to the PLL, eliminating the need for global clock network routing. If you are
using the pll_ref_clk signal to feed other parts of your design, you must use a
global clock network for the signal. If pll_reconfig_soft_reset_en is held low,
the PLL reconfig is not reset during a soft reset, which allows designs targeting
HardCopy II devices to hold the PHY in reset while still accessing the PLL reconfig
block. However, designs targeting Arria GX or Stratix II devices are expected to tie the
pll_reconfig_soft_en
shell to VCC to enable PLL reconfig soft resets.