Altera External Memory PHY Interface - Manual (Page 42)

3–26 Chapter 3: Functional Description—ALTMEMPHY (nonAFI)
Understanding the Testbench
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide © January 2010 Altera Corporation
Write Training Data
A specific pattern of data is written to the memory so that each DQ pin may be
calibrated. The same pattern is written to every DQ pin. The pattern takes the form:
“10101010_11111111_00000000_11111100” from the lowest address location to
the highest address location left to right. Once the memory interface is initialized, a
single write transaction is observed to the memory using the pattern above to write
the same pattern to each DQ bit.
Calibration
When the write training data process is completed, the sequencer then repeatedly
reads the training pattern back from the memory. This action is performed on a per
DQ pin basis, and for all available phase steps supported by the PLL configuration.
The sequencer phase steps through 360° for a full rate controller and through 720° for
a half rate controller. For simulation purposes only, calibration can be performed on
just a single DQ pin, which greatly reduces simulation run time. The sequencer stores
a list of pass and fail training pattern results and when all phase comparisons have
been made, sets the optimum clock phase to be centered in the available window of
results.
Simulation of the calibration cycle cannot be bypassed, but setting it to single bit
calibration speeds up the process significantly.
1
The ALTMEMPHY megafunction only the center of data valid window and read
latency. The amount of internal RAM required to store calibration results therefore, is
significantly reduced compared to earlier versions. The total calibration time is also
reduced.
Functional Memory Use
When training and calibration completes, the ALTMEMPHY sequencer asserts
ctrl_usr_mode_rdy
to the memory controller, which is then copied to the local
interface as the signal local_init_done. Local interface read and write
transactions can now occur.
In the example testbench, the example driver now performs 16 writes followed by 16
reads to incremental address locations spanning column, row and bank locations
using LFSR pattern based on the address being written.