Altera External Memory PHY Interface - Manual (Page 76)

4
–
8
C
ha
pt
er
4:
S
upp
or
t f
o
r Ar
ria
GX,
Ha
rd
Copy
II, S
tr
a
tix
II,
a
n
d
S
tr
a
tix
II GX
De
vic
e
s
DD
R2
/DD
R
SD
RAM
Ex
tern
al
M
emo
ry
PHY
In
terfac
e (A
LT
ME
M
P
HY)
(n
o
n
AF
I) M
eg
afun
cti
on
U
ser Gu
id
e
©
Januar
y
2
010
Al
tera Cor
por
atio
n
Write Datapath
The write datapath logic efficiently transfers data from the HDR memory controller to DDR SDRAM-based memories. The
write datapath logic consists of:
■ DQ and DQ output-enable logic
■ DQS and DQS output-enable logic
■ Data mask (DM) logic
Figure 4–3. ALTMEMPHY Reset Management Block for Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices
PLL
Q
Q SET
CLR
D
Q
Q SET
CLR
D
Q
Q SET
CLR
D
Q
Q SET
CLR
D
Q
Q SET
CLR
D
PLL
reconfig
Q
Q SET
CLR
D
soft_reset_n
global_reset_n
pll_ref_clk
phy_clk_out
reset_request_n
phy_internal_reset_n
areset (active HIGH)
pll_reconfig_reset_ams_n
pll_reconfig_reset_ams_n_r
refclk
c0
locked
reset_master_ams
scan_clk
reset
global_pre_clear
Reset
pipes
PHY resets
pll_reset
pll_locked
Optional
reset_request_n
edge detect and
reset counter
Another
system
clock
clk_divider_reset_n
clk
divider
circuit
phy_clk
reset_n
scan_clk
clk_div_reset_ams_n
clk_div_reset_ams_n_r
pll_reconfig_soft_reset_en
pll_reconfig_reset_n
global_or_soft_reset_n