Altera External Memory PHY Interface - Manual (Page 21)

Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–5
Initialization Timing
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
2. The ALTMEMPHY-controller local interface is the interface between the
ALTMEMPHY megafunction and the controller local interface. All the port names
on this interface are prefixed with ctl_; for example, ctl_init_done. This
interface connects the ALTMEMPHY megafunction to the controller’s local
interface and is of the same type as the local interface, either an Avalon-MM
interface or a native interface. When the calibration process is complete, this
connection becomes a straight-through connection and you have complete control
of the memory controller.
3. The ALTMEMPHY-controller command interface is the interface between the
controller and ALTMEMPHY. All the ports on this interface are prefixed with
ctl_mem_
; for example, ctl_mem_rdata. They are clocked by the phy_clk.
This interface contains the memory control and address signals from the controller
to the memory. The controller also sends write data to, and receives read data
from, the external memory through this interface. All the signals on this interface
are clocked at the phy_clk rate. The ALTMEMPHY megafunction converts
between this clock and the memory interface clock.
4. The fourth interface is between the ALTMEMPHY megafunction and the external
memory devices and consists of the memory address, command, and data pins.
These must be connected directly to the external pins of your Altera FPGA.
Initialization Timing
DDR SDRAM initialization timing is different to DDR2 SDRAM initialization timing.
DDR SDRAM Initialization Timing
f
For DDR2 SDRAM initialization timing, see “DDR2 SDRAM Initialization Timing” on
page 3–7 .
The DDR SDRAM high-performance controller initializes the SDRAM devices by
issuing the following memory command sequence:
■ NOP (for 200 µs, programmable)
■ PCH
■ Extended LMR (ELMR)
■ LMR
■ NOP (for 200 clock cycles, fixed)
■ PCH
■ ARF
■ ARF
■ LMR
Figure 3–4 on page 3–6 shows a typical initialization timing sequence. The length of
time between the reset and the first PCH command should be 200 µs. The value that
you specify for the Memory initialization time at power up (tINIt) setting in the
MegaWizard interface is only used for hardware that you generate. The controller
simulation model is created with a much shorter t
INIT
time to make simulation easier.