Note 1) – Altera External Memory PHY Interface User Manual
Page 37
Chapter 3: Functional Description—ALTMEMPHY (nonAFI)
3–21
ALTMEMPHY Signals
© January 2010
Altera Corporation
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
mem_d
output
MEM_IF_DWIDTH
Memory data bus. D input to QDR II SRAM device.
mem_dm
output
MEM_IF_DM_WIDTH
Memory write select. BWS# input to QDR II SRAM
device.
mem_dq
input
MEM_IF_DWIDTH
Memory data bus. Q output from QDR II SRAM
device.
mem_dqs
input
MEM_IF_DWIDTH /
MEM_IF_DQ_PER_
DQS
Memory read clock high bits (CQ).
mem_dqsn
input
MEM_IF_DWIDTH /
MEM_IF_DQ_PER_
DQS
Memory read clock low bits (CQn).
mem_doff_n
output
1
Memory DLL disable control.
mem_rps_n
output
MEM_IF_CS_WIDTH
Memory read enable signal.
mem_wps_n
output
MEM_IF_CS_WIDTH
Memory write enable signal.
Note to
:
(1) Connected to WYSIWYGS/pad atoms.
Table 3–11. I/O Interface to QDR II+/QDR II SRAM
(Note 1)
(Part 2 of 2)
Signal Name
Type
Width
Description
Table 3–12. Clock and Reset Signals for QDR II+/QDR II SRAM (Part 1 of 2)
Signal Name
Type
Width
Description
global_reset_n
input
1
The asynchronous reset input to the controller. All other
reset signals are derived from resynchronized versions of
this. This signal holds the complete ALTMEMPHY
megafunction, including the PLL, in reset while low.
soft_reset_n
input
1
The asynchronous reset input to reset controller, for
SOPC Builder use, or to be controlled by other system
reset logic. This signal causes a complete reset of the
PHY, but not the PLL in the PHY. In Arria GX, Stratix II,
and Stratix II GX devices, this signal also resets the PLL
reconfiguration block on a falling-edge detection.
phy_clk
output
1
The ALTMEMPHY megafunction half-rate clock provided
to the user. All user inputs and outputs to the
ALTMEMPHY megafunction are synchronous to this clock
in half-rate designs. However, this clock is not used in
full-rate designs.
pll_ref_clk
input
1
The reference clock input to PLL.
reset_phy_clk_n
output
1
Asynchronous reset, that is de-asserted synchronously
with respect to the associated phy_clock clock
domain. Use this to reset any additional user logic on that
clock domain.