Altera External Memory PHY Interface - Manual (Page 58)

3–42 Chapter 3: Functional Description—ALTMEMPHY (nonAFI)
Design Considerations
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide © January 2010 Altera Corporation
its calibration, the ALTMEMPHY megafunction asserts the ctl_usr_mode_rdy,
resynchronization_successful
, local_init_done, and local_ready
signals in DDR3/DDR2/DDR SDRAM interfaces or ctl_usr_mode_rdy and
resynchronization_successful
signals in QDR II+/QDR II SRAM interfaces.
You then have complete control of the memory controller.
f For more information about calibration process, refer to the Calibration section in the
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide.
Local Interface Requirements
The autocalibration logic makes use of the controller to perform its calibration, so
your controller must observe the following requirements.
The controller must have at least one Avalon-MM slave interface or a native interface,
which the ALTMEMPHY megafunction can control during the initial calibration
process. For DDR3 SDRAM and QDR II+/QDR II SRAM variations of the
ALTMEMPHY megafunction, only the Avalon-MM local interface is supported. When
calibration is complete, no further access to this interface is required by the
ALTMEMPHY megafunction.
The memory burst length can be two, four, or eight for DDR SDRAM devices; the
memory burst length can be four or eight for DDR2 SDRAM devices; DDR3 SDRAM
burst lengths can be set at either four or eight, when using the Altera high-
performance controller. The QDR II+/QDR II SRAM variations of the ALTMEMPHY
megafunction only support burst length of four. For a half-rate controller, the memory
clock runs twice as fast as the clock provided to the local interface; so data buses on
the local interface are four times as wide as the memory data bus. For a full-rate
controller, the memory clock runs at the same speed as the clock provided to the local
interface, so the data buses on the local interface are two times as wide as the memory
data bus. Each read or write request on the local interface fits into a single memory
read or write command on the memory interface, simplifying the controller design.
1 The ALTMEMPHY megafunction with the nonAFI does not support burst lengths of
eight.
DDR2/DDR SDRAM Half-Rate Controller
The following sections describe the handshake mechanism between the read
commands and read data for the controller in a DDR2/DDR SDRAM interface.
f
For more information about the timing diagrams of a DDR2 SDRAM
High-Performance controller, refer to the Timing Diagrams chapter in the
DDR and
DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide.
1 The behavior of ctl_* signals is the same as local_* signals during calibration.
These signals switch to local_* signals after calibration.