Altera External Memory PHY Interface - Manual (Page 57)

Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–41
Design Considerations
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
Design Considerations
This section discusses the design considerations for nonAFI designs.
Clocks and Resets
The ALTMEMPHY megafunction automatically generates a PLL instance, but you
must still provide the reference clock input (pll_ref_clk) with a clock of the
frequency that you specified in the MegaWizard interface. An active-low global reset
input is also provided, which you can de-assert asynchronously. The clock and reset
management logic synchronizes this reset to the appropriate clock domains inside the
ALTMEMPHY megafunction. A clock output, which is half the memory clock
frequency for a half-rate controller and the same as the memory clock for a full-rate
controller, is provided (phy_clk or aux_half_rate_clk) and all inputs and
outputs of the ALTMEMPHY megafunction are synchronous to this clock. An
active-low synchronous reset is also provided (reset_phy_clk_n). This
reset_phy_clk_n
signal is synchronously de-asserted with respect to the phy_clk
clock domain and can reset any additional user logic on that clock domain. In
addition, there is a full rate clock (aux_full_rate_clk) output available to use
anywhere else in your design. This clock is derived from the mem_clk_2x PLL
output signal.
Calibration Process Requirements
As the autocalibration logic makes use of the controller to perform its calibration, you
should follow these guidelines at power-up. When the global reset
(global_reset_n) is released, the clock management logic waits for the PLL to lock
and then releases the reset to the rest of the logic, including the controller. As the PLL
locked output is gated inside the PLL, for approximately the first 10,000 cycles (by this
time the PLL-locked output is stable) of the PLL reference clock, there is no activity at
this time. When the reset to the controller (reset_phy_clk_n) is released, the
controller begins its normal memory initialization sequence. When complete, the
controller indicates to the ALTMEMPHY megafunction that it is ready to accept the
calibration writes and reads by asserting the ctl_init_done and ctl_ready
signals in DDR3/DDR2/DDR SDRAM interfaces. (There are no such signals in
QDR II+/QDR II SRAM interfaces, as the SRAM device does not need an initialization
sequence other than initializing the memory DLL.) The auto-calibration logic then
issues a series of writes and reads to the external memory. You do not have access to
the memory controller during this period. When the autocalibration logic completes
rsu_grt_one_dvw_err
(Calibration failed due to more than one valid
window)
If the RSU sweeps the resynchronization clock across every phase and sees
multiple data valid windows, this is indicative of unexpected read data
(random bit errors) or an incorrectly configured PLL which must be
resolved. Calibration has failed and this output is set to 1.
rsu_multiple_valid_latencies_
err
(Calibration failed due to more than two read
latencies)
If the RSU sweeps the resynchronization clock across every phase and sees
valid data at more than two different latencies, then calibration fails and this
output is set to 1.
Table 3–17. Signals for Calibration Status
Signal Description