Figure 3–15 – Altera External Memory PHY Interface User Manual

Page 66

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3–50

Chapter 3: Functional Description—ALTMEMPHY (nonAFI)

Design Considerations

External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide

© January 2010

Altera Corporation

For DDR SDRAM, the write latency is fixed at one memory clock cycle, but for DDR2
SDRAM, this value changes with the read CAS latency. As the controller is running at
half the rate of the memory clock, a latency change of one controller clock cycle is
actually two memory clock cycles. The ALTMEMPHY megafunction allows you to
dynamically insert an extra memory clock of delay in the address and command path
to compensate for this. The insertion of delay is controlled by the ADDR_CMD_ADD_1T
parameter and the ctl_add_1t_ac_lat signal. If ADDR_CMD_ADD_1T is set to the

Figure 3–15. Write Commands and Write Data (Full-Rate Controller)

Notes to

Figure 3–15

:

(1) The DDR command shows the command comprised of the command signals (ctl_mem_ras_n_h, ctl_mem_cas_n_h, and

ctl_mem_we_n_h)

seen at the ALTMEMPHY input. There can be more than one clock cycle of NOP between ACT to RD depending on the value

of t

RCD

parameter of your memory device.

(2) The DDR command shows the command comprised of the command signals (mem_ras_n_h, mem_cas_n_h, and mem_we_n_h) seen at

the memory interface.

phy_clk

ctl_mem_cs_n_h

ctl_mem_addr_h

ctl_mem_odt_h

DDR Command

(1)

mem_clk

mem_addr

mem_odt

mem_dqs

mem_dq

ctl_mem_wdata_valid

DDR Command

(2)

mem_cs_n

PHY Command Input

PHY Write Data Input

PHY Command Output

NOP

WR NOP

local_write_req

ctl_mem_dqs_burst

WR NOP WR NOP WR NOP

0000

0008 0000 000c 0000 0010 0000

NOP

WR NOP WR NOP WR NOP WR

NOP

0004

0000

0000 0008 0000 000c 0000

NOP WR

0010 0000

000000

1... 4... 3...

7... 0... f... 0...

0... c... 0...

1... 3... 2... 7...

e... 8... 000000

0000

0...

0... 1... 0... 1...

1... 0... 1...

1... 0... 1... 0...

0... 1...

0000

PHY Write Data Output

mem_dqs

ctl_mem_wdata

WR NOP

0004 0000

0000

0...

0...

0... 1...

1...

1... 0... 1...

0... 1... 0...

0... 000000

808bdae4ec55833a

8e7a

1...

0...

0...

473d

02f5

01f4

08f3

04f7

20eb

10fb

8e7a

40cb

808bdae4ec55833a

0...

0...

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