Altera External Memory PHY Interface - Manual (Page 22)

3–6 Chapter 3: Functional Description—ALTMEMPHY (nonAFI)
Initialization Timing
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide © January 2010 Altera Corporation
1 Do not set tINIT to zero.
The following sequence corresponds with the numbered items in Figure 3–4 .
1. A PCH command is sent to all banks by setting the precharge pin, the address bit
a[10] , or a[8] high.
2. An ELMR command is issued to enable the internal delay-locked loop (DLL) in the
memory devices. An ELMR command is an LMR command with the bank address
bits set to address the extended mode register.
3. An LMR command sets the operating parameters of the memory such as CAS
latency and burst length. This LMR command also resets the internal memory
device DLL. The DDR SDRAM high-performance controller allows 200 clock
cycles to elapse after a DLL reset and before it issues the next command to the
memory.
4. A further PCH command places all the banks in their idle state.
5. Two ARF commands must follow the PCH command.
6. The final LMR command programs the operating parameters without resetting the
DLL.
After issuing the final LMR command, the memory controller hands over control of
the memory to the ALTMEMPHY megafunction to allow it to carry out its calibration
process.
When the ALTMEMPHY megafunction has finished calibrating, the memory
controller asserts the local_init_done signal, which shows that it has initialized
the memory devices.
Figure 3–4. DDR SDRAM Device Initialization Timing
clk
ddr_cke
ddr_a
ddr_ba
ddr_cs_n
ddr_ras_n
ddr_cas_n
ddr_we_n
local_init_done
0 0
0 1 0 1
0 0 0 0 0 0 0 0
[1] [2] [3] [4] [6] [5] [5]
200 clock cycles
Key:
P = PCH
L = LMR
A = ARF
DDR Command P L L P A A L L