Altera External Memory PHY Interface - Manual (Page 70)

4–2 Chapter 4: Support for Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices
DDR2/DDR SDRAM
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide © January 2010 Altera Corporation
Figure 4–1 shows the order of the functions performed by the read datapath, along
with the frequency at which the read data is handled.
Data Capture and Resynchronization
Data capture and resynchronization is the process of capturing the read data (DQ)
with the DQS strobe and re-synchronizing the captured data to an internal
free-running full-rate clock supplied by the enhanced phase-locked loop (PLL).
The resynchronization clock is an intermediate clock whose phase shift is determined
during the calibration stage.
Timing constraints ensure that the data resynchronization registers are placed close to
the DQ pins to achieve maximum performance. Timing constraints also further limit
skew across the DQ pins. The captured data (rdata_2x_p and rdata_2x_n) is
synchronized to the resynchronization clock (resync_clk_2x), see
Figure 4–1 .
Data Demultiplexing
Data demultiplexing is the process of SDR data into HDR data. Data demultiplexing
is required to bring the frequency of the resynchronized data down to the frequency
of the system clock, so that data from the external memory device can ultimately be
brought into the FPGA DDR2/DDR SDRAM controller clock domain. Before data
capture, the data is DDR and n-bit wide. After data capture, the data is SDR and 2n-bit
wide. After data demuxing, the data is HDR of width 4n-bits wide. The system clock
frequency is half the frequency of the memory clock.
Demultiplexing is achieved using a dual-port memory with a 2n-bit wide write-port
operating on the resynchronization clock (SDR) and a 4n-bit wide read-port operating
on the PHY clock (HDR). The basic principle of operation is that data is written to the
memory at the SDR rate and read from the memory at the HDR rate while
incrementing the read- and write-address pointers. As the SDR and HDR clocks are
generated, the read and write pointers are continuously incremented by the same
PLL, and the 4n-bit wide read data follows the 2n-bit wide write data with a constant
latency.
Figure 4–1. DDR2/DDR SDRAM Read Datapath in Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices
SDR SDR/HDR DDR
D Q D Q
Data Capture
IOE
D Q D Q
D Q
Data Resynchronization Data Demux and Alignment
rdata_1x[4n]
wr_data[2n] rd_data[4n]
wr_clk rd_clk
FIFO
phy_clk_1x
rdata_2x_p[n]
rdata_2x_n[n]
resync_clk_2x
DQ[n]
DQS