Altera External Memory PHY Interface - Manual (Page 53)

Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–37
Functional Simulation—the ModelSim Wave and Transcript Window
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
1 Until the completion of the calibration phase, the local interface remains static and all
transactions take place over the control interface. Additional signals of interest are
added to the wave view.
1 For simulation purposes, the ALTMEMPHY megafunction allows calibration of a
single DQ pin. If you do not enable this option, then the time required for the
calibration phase of the simulation is multiplied by the number of DQ pins used in
your actual memory controller instance. To enable this option, select Quick
Calibration
under Auto-Calibration Simulation Options list at the Memory Settings
tab in the Parameter Settings page.
Functional Memory Use Stage
Once the calibration stage completes, indicated by the signals local_init_done
and ctl_usr_mode_rdy, then the functional memory use stage begins.
The example driver, which is generated by the MegaWizard Plug-In Manager, is clear
text HDL in the language of your choice. It can be used to test a custom controller and
ALTMEMPHY megafunction combination. It performs a series of writes to the
external memory, followed by a series of reads to the same locations, and compares
the read and write data.
This comparison results in dynamic “pass not fail per byte” (pnf_per_byte) signals,
and a latched combined pass not fail (pnf, 1=pass 0=fail) signal. Each completed series
of writes and reads is signaled via the test_complete signal, and then the test
repeats.
1 The example testbench stops when either test_complete is asserted or when
200,000 mem_clk cycles after the t
INIT
time.
In Figure 3–11 on page 3–38 , the series of writes followed by reads can be seen on both
the local and memory interfaces, together with the test complete signals.
As the data written to the memory is simply an LFSR pattern, the example driver is
able to generate expected read data from the memory to compare with that previously
written to the same address. The data on the read data bus should match that on the
write data bus during the read process.