Altera External Memory PHY Interface - Manual (Page 79)

Chapter 4: Support for Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices 4–11
DDR2/DDR SDRAM
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
Full-Rate Support
The following section discusses full-rate support for Arria GX, HardCopy II, Stratix II,
and Stratix II GX devices.
Read Datapath
The full-rate datapath is similar to the half-rate datapath. The full-rate datapath also
consists of a RAM with the same width as the data input (just like that of the
half-rate), but the width on the data output of the RAM is half that of the half-rate
PHY. The function of the RAM is to transfer the read data from the resynchronization
clock domain to the system clock domain.
Postamble Protection
The postamble protection is the same as the half-rate support.
Clock and Reset Management
For full-rate clock and reset management refer to. The PLL is configured exactly in the
same way as in half-rate designs. The PLL information and restriction from half-rate
designs also applies.
1
The phy_clk_1x clock is now full-rate, despite the “1x” naming convention.
You must choose a PLL and PLL input clock pin that are located on the same side of
the memory interface to ensure minimal jitter. Cascaded PLLs are not recommended
for DDR2/DDR SDRAM interfaces as jitter can accumulate with the use of cascaded
PLLs causing the memory output clock to violate the memory device jitter
specification. Also, ensure that the input clock to the PLL is stable before the PLL
locks. If not, you must perform a manual PLL reset and relock the PLL to ensure that
the phase relationship between all PLL outputs are properly set. The PLL restrictions
in half-rate designs also applies to full-rate designs.
Write Datapath
The write datapath is similar to the half-rate PHY. The IOE block is identical to the
half-rate PHY. The latency of the write datapath in the full-rate PHY is less than in the
half-rate PHY because the full-rate PHY does not have the half-rate-to-full-rate
conversion logic.
Address and Command Datapath
The address and command datapath for full-rate designs is similar to half-rate
designs, except that the address and command signals are all asserted for one
memory clock cycle only (1T signaling).