Altera External Memory PHY Interface - Manual (Page 72)

4–4 Chapter 4: Support for Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices
DDR2/DDR SDRAM
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide © January 2010 Altera Corporation
Clock Management
The ability of the ALTMEMPHY megafunction to work out the optimum
resynchronization clock phase during calibration, and to track the system voltage and
temperature (VT) variations. Clock management is done by phase-shifting the clocks
relative to each other.
Clock management circuitry is implemented by using the following device resources:
■ PLL
■ PLL reconfiguration
■ DLL
PLL
The ALTMEMPHY MegaWizard interface automatically generates an ALTPLL
megafunction instance. The ALTPLL megafunction is responsible for generating the
different clock frequencies and relevant phases used within the ALTMEMPHY
megafunction.
The minimum PHY requirement is to have 16 phases of the highest frequency clock.
The PLL uses With no compensation operation mode to minimize jitter.
You must choose a PLL and PLL input clock pin that are located on the same side of
the memory interface to ensure minimal jitter. Cascaded PLLs are not recommended
for DDR2/DDR SDRAM interfaces as jitter can accumulate with the use of cascaded
PLLs causing the memory output clock to violate the memory device jitter
specification. Also, ensure that the input clock to the PLL is stable before the PLL
locks. If not, you must perform a manual PLL reset and relock the PLL to ensure that
the phase relationship between all PLL outputs are properly set.
1 If the design cascades PLLs, the source (upstream) PLL should have a low-bandwidth
setting; the destination (downstream) PLL should have a high-bandwidth setting.
Adjacent PLLs cascading is recommended to reduce clock jitters.
f
For more information about the VCO frequency range and the available phase shifts,
refer to the PLLs in Stratix II and Stratix II GX Devices chapter in the respective device
family handbook.