Altera External Memory PHY Interface - Manual (Page 69)

© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
4. Support for Arria GX, HardCopy II,
Stratix II, and Stratix II GX Devices
The following sections describe the ALTMEMPHY megafunction support for
Arria GX, Stratix II, and Stratix II GX devices.
1 HardCopy ® II ASIC device support is similar to that of the Stratix II FPGA family.
However, some design considerations are specific to the HardCopy II device family.
The ALTMEMPHY megafunction does not natively support a memory interface that
spans on multiple sides of the device in these device families, because the memory
interface pins that are connected to the DLL are only available on the top and bottom
of the device. In silicon, you can route the DLL control settings from one side of the
device to another side of the device via local routing. To perform local routing, you
must register the DLL control settings and to minimize the arrival skew of the DLL
control settings at the other side of the device. However, this method has not been
characterized and its performance is unknown. Therefore, this implementation is
discouraged.
DDR2/DDR SDRAM
Arria GX, HardCopy II, Stratix II, and Stratix II GX devices support both full-rate and
half-rate DDR2/DDR SDRAM PHYs.
Half-Rate Support
The following section discusses half-rate support for DDR2/DDR SDRAM for
Arria GX, HardCopy II, Stratix II, and Stratix II GX devices.
Read Datapath
The read datapath logic is responsible for capturing data sent by the memory device
and subsequently aligning the data back to the system clock domain. The following
functions are performed by the read datapath:
1. Data capture and resynchronization
2. Data demultiplexing
3. Data alignment