Document Outline

• Title - Speedster22i Macro Cell Library
  • ChapterTitlePreface - Preface
    • Heading1 - Introduction
    • Heading1 - Cell Naming Conventions
      • Heading2 - Register Naming Conventions
      • Heading2 - I/O Cell Naming Conventions
    • Heading1 - Conventions Used in this Guide
  • ChapterTitle - Chapter 1 – I/O Cells
    • Table - Table 1-1: Supported Single-Ended Voltage Standards
    • Table - Table 1-2: Supported Differential Voltage Standards
    • Heading1 - IOPAD
      • Heading2 - Bidirectional I/O Pad
        • Figure - Figure 1-1: IOPAD Logic Symbol
        • Table - Table 1-3: Ports
        • Table - Table 1-4: Parameters
        • Table - Table 1-5: Output Function Table
        • Table - Table 1-6: Input Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - IOPAD_D
      • Heading2 - Bidirectional Registered I/O Pad with Asynchronous or Synchronous Set/Reset
        • Figure - Figure 1-2: IOPAD_D Logic Symbol
        • Table - Table 1-7: Ports
        • Table - Table 1-8: Parameters
        • Table - Table 1-9: Output Function Table (txregmode = ”reg”, oeregmode = “reg”, rstmode = “async”)
        • Table - Table 1-10: Output Function Table (txregmode = ”reg”, oeregmode = “reg”, rstmode = “sync”)
        • Table - Table 1-11: Input Function table (rxregmode = “reg”)
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - IOPAD_D2
      • Heading2 - Bidirectional DDR I/O Pad with Asynchronous or Synchronous Set/ Reset
        • Figure - Figure 1-3: IOPAD_D2 Logic Symbol
        • Table - Table 1-12: Ports
        • Table - Table 1-13: Parameters
        • Figure - Figure 1-4: IOPAD_D2 Output Timing Diagram (assumes txdata_en = 1’b1)
        • Figure - Figure 1-5: IOPAD_D2 Input Timing Diagram (assumes rxdata_en = 1’b1)
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - IPAD
      • Heading2 - Non-Registered Input Pad
        • Figure - Figure 1-6: IPAD Logic Symbol
        • Table - Table 1-14: Ports
        • Table - Table 1-15: Parameters
        • Table - Table 1-16: Input Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - IPAD_D
      • Heading2 - Registered Input Pad with Asynchronous or Synchronous Set/Reset
        • Figure - Figure 1-7: IPAD_D Logic Symbol
        • Table - Table 1-17: Ports
        • Table - Table 1-18: Parameters
        • Table - Table 1-19: Input Function table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - IPAD_D2
      • Heading2 - DDR Input Pad with Asynchronous or Synchronous Set/Reset
        • Figure - Figure 1-8: IPAD_D2 Logic Symbol
        • Table - Table 1-20: Ports
        • Table - Table 1-21: Parameters
        • Figure - Figure 1-9: IPAD_D2 Input Timing Diagram (assumes data_en = 1’b1)
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - IPAD_DIFF
      • Heading2 - Non-Registered Differential Input Pad
        • Figure - Figure 1-10: IPAD_DIFF Logic Symbol
        • Table - Table 1-22: Ports
        • Table - Table 1-23: Parameters
        • Table - Table 1-24: Input Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - IPAD_DIFFD
      • Heading2 - Registered Differential Input Pad with Asynchronous or Synchronous Set/Reset
        • Figure - Figure 1-11: IPAD_DIFFD Logic Symbol
        • Table - Table 1-25: Ports
        • Table - Table 1-26: Parameters
        • Table - Table 1-27: Input Function table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - IPAD_DIFFD2
      • Heading2 - DDR Differential Input Pad with Asynchronous or Synchronous Set/ Reset
        • Figure - Figure 1-12: IPAD_DIFFD2 Logic Symbol
        • Table - Table 1-28: Ports
        • Table - Table 1-29: Parameters
        • Figure - Figure 1-13: IPAD_DIFFD2 Input Timing Diagram (assumes data_en = 1’b1)
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - OPAD
      • Heading2 - Non-Registered Output Pad
        • Figure - Figure 1-14: OPAD Logic Symbol
        • Table - Table 1-30: Ports
        • Table - Table 1-31: Parameters
        • Table - Table 1-32: Output Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - OPAD_D
      • Heading2 - Registered Output Pad with Asynchronous or Synchronous Set/Reset
        • Figure - Figure 1-15: OPAD_D Logic Symbol
        • Table - Table 1-33: Ports
        • Table - Table 1-34: Parameters
        • Table - Table 1-35: Output Function Table (rstmode = “async”)
        • Table - Table 1-36: Output Function Table (rstmode = “sync”)
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - OPAD_D2
      • Heading2 - DDR Output Pad with Asynchronous or Synchronous Set/Reset
        • Figure - Figure 1-16: OPAD_D2 Logic Symbol
        • Table - Table 1-37: Ports
        • Table - Table 1-38: Parameters
        • Figure - Figure 1-17: OPAD_D2 Output Timing Diagram (assumes data_en = 1’b1)
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - OPAD_DIFF
      • Heading2 - Non-Registered Differential Output Pad
        • Figure - Figure 1-18: OPAD_DIFF Logic Symbol
        • Table - Table 1-39: Ports
        • Table - Table 1-40: Parameters
        • Table - Table 1-41: Output Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - OPAD_DIFFD
      • Heading2 - Registered Differential Output Pad with Asynchronous or Synchronous Set/Reset
        • Figure - Figure 1-19: OPAD_DIFFD Logic Symbol
        • Table - Table 1-42: Ports
        • Table - Table 1-43: Parameters
        • Table - Table 1-44: Output Function Table (rstmode = “async”)
        • Table - Table 1-45: Output Function Table (rstmode = “sync”)
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - OPAD_DIFFD2
      • Heading2 - DDR Differenctial Output Pad with Asynchronous or Synchronous Set/Reset
        • Figure - Figure 1-20: OPAD_DIFFD2 Logic Symbol
        • Table - Table 1-46: Ports
        • Table - Table 1-47: Parameters
        • Figure - Figure 1-21: OPAD_DIFFD2 Output Timing Diagram (assumes data_en = 1’b1)
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - TPAD
      • Heading2 - Non-Registered Tristate Output Pad
        • Figure - Figure 1-22: TPAD Logic Symbol
        • Table - Table 1-48: Ports
        • Table - Table 1-49: Parameters
        • Table - Table 1-50: Output Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - TPAD_D
      • Heading2 - Registered Tristate Output Pad with Asynchronous or Synchronous Set/Reset
        • Figure - Figure 1-23: TPAD_D Logic Symbol
        • Table - Table 1-51: Ports
        • Table - Table 1-52: Parameters
        • Table - Table 1-53: Output Function Table (rstmode = “async”)
        • Table - Table 1-54: Output Function Table (rstmode = “sync”)
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
  • ChapterTitle - Chapter 2 – Registers
    • Heading1 - Naming Convention
    • Heading1 - DFF
      • Heading2 - Positive Clock Edge D-Type Register
        • Figure - Figure 2-1: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-1: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-2: Parameters
        • Heading3 - init
        • Table - Table 2-3: Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFE
      • Heading2 - Positive Clock Edge D-Type Register with Clock Enable
        • Figure - Figure 2-2: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-4: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-5: Parameters
        • Heading3 - init
        • Table - Table 2-6: Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFEC
      • Heading2 - Positive Clock Edge D-Type Register with Clock Enable and Synchronous Clear
        • Figure - Figure 2-3: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-7: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-8: Parameters
        • Heading3 - init
        • Table - Table 2-9: Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFEP
      • Heading2 - Positive Clock Edge D-Type Register with Clock Enable and Synchronous Preset
        • Figure - Figure 2-4: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-10: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-11: Parameters
        • Heading3 - init
        • Table - Table 2-12: Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFER
      • Heading2 - Positive Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Reset
        • Figure - Figure 2-5: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-13: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-14: Parameters
        • Heading3 - init
        • Heading3 - sr_assertion
        • Table - Table 2-15: DFFER Function Table when sr_assertion = “unclocked”
        • Table - Table 2-16: DFFER Function Table when sr_assertion = “clocked”
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFES
      • Heading2 - Positive Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Set
        • Figure - Figure 2-6: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-17: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-18: Parameters
        • Heading3 - init
        • Heading3 - sr_assertion
        • Table - Table 2-19: DFFES Function Table when sr_assertion = “unclocked”
        • Table - Table 2-20: DFFES Function Table when sr_assertion = “clocked”
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFN
      • Heading2 - Negative Clock Edge D-Type Register
        • Figure - Figure 2-7: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-21: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-22: Parameters
        • Heading3 - init
        • Table - Table 2-23: Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFNEC
      • Heading2 - Negative Clock Edge D-Type Register with Clock Enable and Synchronous Clear
        • Figure - Figure 2-8: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-24: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-25: Parameters
        • Heading3 - init
        • Table - Table 2-26: Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFNEP
      • Heading2 - Negative Clock Edge D-Type Register with Clock Enable and Synchronous Preset
        • Figure - Figure 2-9: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-27: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-28: Parameters
        • Heading3 - init
        • Table - Table 2-29: Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFNER
      • Heading2 - Negative Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Reset
        • Figure - Figure 2-10: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-30: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-31: Parameters
        • Heading3 - init
        • Heading3 - sr_assertion
        • Table - Table 2-32: DFFNER Function Table when sr_assertion = “unclocked”
        • Table - Table 2-33: DFFNER Function Table when sr_assertion = “clocked”
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFNES
      • Heading2 - Negative Clock Edge D-Type Register with Clock Enable and Asynchronous/Synchronous Set
        • Figure - Figure 2-11: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-34: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-35: Parameters
        • Heading3 - init
        • Heading3 - sr_assertion
        • Table - Table 2-36: DFFNES Function Table when sr_assertion = “unclocked”
        • Table - Table 2-37: DFFNES Function Table when sr_assertion = “clocked”
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFNR
      • Heading2 - Negative Clock Edge D-Type Register with Asynchronous Reset
        • Figure - Figure 2-12: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-38: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-39: Parameters
        • Heading3 - init
        • Heading3 - sr_assertion
        • Table - Table 2-40: Function Table when sr_assertion = “unclocked’
        • Table - Table 2-41: Function Table when sr_assertion = “clocked’
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFNS
      • Heading2 - Negative Clock Edge D-Type Register with Asynchronous Set
        • Figure - Figure 2-13: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-42: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-43: Parameters
        • Heading3 - init
        • Heading3 - sr_assertion
        • Table - Table 2-44: Function Table when sr_assertion = “unclocked’
        • Table - Table 2-45: unction Table when sr_assertion = “clocked’
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFR
      • Heading2 - Positive Clock Edge D-Type Register with Asynchronous Reset
        • Figure - Figure 2-14: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-46: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-47: Parameters
        • Heading3 - init
        • Heading3 - sr_assertion
        • Table - Table 2-48: Function Table when sr_assertion = “unclocked’
        • Table - Table 2-49: Function Table when sr_assertion = “clocked’
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - DFFS
      • Heading2 - Positive Clock Edge D-Type Register with Asynchronous Set
        • Figure - Figure 2-15: Logic Symbol
      • Heading2 - Pins
        • Table - Table 2-50: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 2-51: Parameters
        • Heading3 - init
        • Heading3 - sr_assertion
        • Table - Table 2-52: Function Table when sr_assertion = “unclocked’
        • Table - Table 2-53: Function Table when sr_assertion = “clocked’
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
  • ChapterTitle - Chapter 3 – Logic Functions
    • Heading1 - MUX2
      • Heading2 - Two Input Multiplexer Gate
        • Figure - Figure 3-1: Logic Symbol
      • Heading2 - Pins
        • Table - Table 3-1: Pin Descriptions
        • Table - Table 3-2: Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
  • ChapterTitle - Chapter 4 – Lookup Table (LUT) Functions
    • Heading1 - LUT4
      • Heading2 - Four Input Lookup Table
        • Figure - Figure 4-1: Logic Symbol
      • Heading2 - Pins
        • Table - Table 4-1: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 4-2: Parameters
        • Heading3 - lut_function
        • Table - Table 4-3: Function Table
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
  • ChapterTitle - Chapter 5 – Arithmetic Functions
    • Heading1 - ALU
      • Heading2 - Two Input Adder / Subtractor with Programmable Load
        • Figure - Figure 5-1: Logic Symbol
      • Heading2 - Pins
        • Table - Table 5-1: Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 5-2: Parameters
        • Heading3 - invert_b
        • Table - Table 5-3: Function Table When invert_b = 1’b0.
        • Table - Table 5-4: Function Table When invert_b = 1’b1.
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
  • ChapterTitle - Chapter 6 – Memories
    • Heading1 - BRAM80K
      • Heading2 - 80k-bit Dual-Port Memory
        • Figure - Figure 6-1: Logic Symbol
        • Figure - Figure 6-2: BRAM80K Block Diagram (Per Port)
      • Heading2 - BRAM80K Pins
        • Table - Table 6-1: BRAM80K Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 6-2: BRAM80K Parameters
        • Heading3 - porta_read_width(portb_read_width)
        • Heading3 - porta_write_width(portb_write_width)
        • Heading3 - porta_write_mode(portb_write_mode)
        • Heading3 - porta_clock_polarity(portb_clock_polarity)
        • Heading3 - porta_peval(portb_peval)
        • Heading3 - porta_latch_rstval(portb_latch_rstval)
        • Heading3 - porta_en_out_reg(portb_en_out_reg)
        • Heading3 - porta_reg_rstval(portb_reg_rstval)
        • Heading3 - porta_regce_priority(portb_regce_priority)
        • Heading3 - porta_initval(portb_initval)
        • Table - Table 6-3: Relationship of porta_initval(portb_initval) bit positions to douta,doutpa,doutpxa (doutb,doutpb,doutpxb)
        • Heading3 - porta_srval(portb_srval)
        • Table - Table 6-4: Relationship of porta_srval(portb_srval) bit positions to douta,doutpa,doutpxa (doutb,doutpb,doutpxb)
        • Heading3 - mem_init_file
        • Heading3 - initd_000 – initd_255
        • Heading3 - initp_00 – initp_31
        • Heading3 - initpx_00 – initpx_31
      • Heading2 - Memory Organization and Data Input / Output Pin Assignments
        • Table - Table 6-5: Valid Port A Width Versus Port B Width Combinations per port for n x 5 width modes
        • Table - Table 6-6: Valid Port A Width Versus Port B Width Combinations per port for n x 9 width modes
        • Table - Table 6-7: Valid Port A Width Versus Write Port B Combinations per port for n x 2 width modes
        • Table - Table 6-8: dina(dinb) bit assignments per porta_write_width(portb_write_width) values
        • Table - Table 6-9: Write Enable to Data Input Bus Mapping per Write Port Width
        • Table - Table 6-10: douta(doutb) bit assignments per porta_read_width(portb_read_width) values
        • Table - Table 6-11: BRAM80K Address Bus Mapping (Per Port)
        • Table - Table 6-12: Mapping of Word Sizes to the Native 2048x40 Memory Locations
      • Heading2 - Read and Write Operations
        • Heading3 - Read Operation
        • Heading3 - Write Operation
        • Table - Table 6-13: BRAM Output Function Table for Latched Mode (Assumes active-high clock, port enable, and latch reset value)
        • Table - Table 6-14: BRAM Output Function Table for Registered Mode (Assumes active-high clock, output register clock enable, and output register reset)
        • Heading3 - Simultaneous Memory Operations
        • Heading3 - Timing Diagrams
        • Figure - Figure 6-3: Write-First, Latched Mode Timing Diagram
        • Figure - Figure 6-4: Write-First, Registered Mode Timing Diagram
        • Figure - Figure 6-5: No-Change, Latched Mode Timing Diagram
        • Figure - Figure 6-6: No-Change, Registered Mode Timing Diagram
        • Heading3 - Support for Read-First (Read-Before-Write) Memory Operations
      • Heading2 - Memory Initialization
      • Heading2 - BRAM80K Verilog Instantiation Template
      • Heading2 - BRAM80K VHDL Instantiation Template
    • Heading1 - BRAM80KFIFO
      • Heading2 - 80k-bit FIFO Memory
        • Figure - Figure 6-7: Logic Symbol
        • Figure - Figure 6-8: BRAM80KFIFO Block Diagram
        • Table - Table 6-15: BRAM80KFIFO Pin Description
      • Heading2 - Parameters
        • Table - Table 6-16: BRAM80KFIFO Parameters
        • Heading3 - sync_mode
        • Heading3 - write_width
        • Table - Table 6-17: FIFO write_width versus Maximum Write Depth
        • Table - Table 6-18: din, dinp, dinpx bit assignments per write_width values
        • Heading3 - read_width
        • Table - Table 6-19: FIFO read_width versus Maximum Read Depth
        • Table - Table 6-20: dout bit assignments per read_width values
        • Table - Table 6-21: Valid Read Width Versus Write Width Combinations per port for n x 5 width modes
        • Table - Table 6-22: Valid Read Width Versus Write Width Combinations per port for n x 9 width modes
        • Table - Table 6-23: Valid Read Width Versus Write Width Combinations per port for 2n width modes
        • Heading3 - fwft
        • Heading3 - en_out_reg
        • Heading3 - reg_initval
        • Table - Table 6-24: Relationship of reg_initval bit positions to dout,doutp,doutpx
        • Heading3 - reg_srval
        • Table - Table 6-25: Relationship of reg_srval bit positions to dout,doutp,doutpx
        • Heading3 - reg_rstval
        • Heading3 - wrrst_rstval
        • Heading3 - wrrst_input_mode
        • Table - Table 6-26: wrrst_input_mode Parameter Mapping.
        • Figure - Figure 6-9: Read and Write Pointer Reset Input Selection Block Diagram
        • Table - Table 6-27: Reset Usage Model for wrrst and rdrst Inputs
        • Heading3 - wrrst_sync_stages
        • Table - Table 6-28: Mapping wrrst_sync_stages Parameter Settings to Synchronization Stage Depth
        • Heading3 - wrptr_sync_stages
        • Table - Table 6-29: Mapping wrptr_sync_stages Parameter Settings to Synchronization Stage Depth
        • Heading3 - rdrst_rstval
        • Heading3 - rdrst_input_mode
        • Table - Table 6-30: rdrst_input_mode Parameter Mapping.
        • Heading3 - rdrst_sync_stages
        • Table - Table 6-31: Mapping rdrst_sync_stages Parameter Settings to Synchronization Stage Depth
        • Heading3 - rdptr_sync_stages
        • Table - Table 6-32: Mapping rdptr_sync_stages Parameter Settings to Synchronization Stage Depth
        • Heading3 - wrcount_sync_mode
        • Heading3 - rdcount_sync_mode
        • Heading3 - afull_offset
        • Table - Table 6-33: Condition to Assert almost_full Flag based on afull_offset Parameter Assignment
        • Heading3 - aempty_offset
        • Table - Table 6-34: Condition to Assert almost_empty Flag based on afull_offset Parameter Assignment
        • Heading3 - wren_polarity_sel
        • Heading3 - rden_polarity_sel
        • Heading3 - en_rd_when_empty
        • Heading3 - en_wr_when_full
      • Heading2 - Read and Write Count Outputs
        • Heading3 - Write Count Output
        • Figure - Figure 6-10: Write Pointer Synchronizer Block Diagram
        • Heading3 - Read Count Output
        • Figure - Figure 6-11: Read Pointer Synchronizer Block Diagram
      • Heading2 - Status Flags
        • Heading3 - Empty Flag
        • Heading3 - Almost Empty Flag
        • Heading3 - Full Flag
        • Heading3 - Almost Full Flag
        • Heading3 - Write Error Flag
        • Heading3 - Read Error Flag
      • Heading2 - Flag Latency
        • Table - Table 6-35: FIFO Pointers and Status Flag Clock Domain Assignments
        • Table - Table 6-36: Pointers Used for FIFO Flag Calculations
        • Table - Table 6-37: Empty and Almost Empty Flag Latency in Terms of Read Clock Cycles
        • Table - Table 6-38: Full and Almost Full Flag Latency in Terms of Write Clock Cycles
      • Heading2 - Optional Output Register
        • Table - Table 6-39: Function Table for Optional Output Register (Assumes active-high rdclk, active-high outregce, and active-high rstreg)
      • Heading2 - FIFO Operational Modes
        • Heading3 - Asynchronous FIFO Operation
        • Heading3 - Synchronous FIFO Operation
      • Heading2 - FIFO Operations
        • Heading3 - Basic Mode FIFO Reset Operation
        • Table - Table 6-40: Parameter Settings Required for Basic Mode FIFO Reset Operation
        • Figure - Figure 6-12: Basic Mode FIFO Reset Timing Diagram
        • Heading3 - Advanced Mode FIFO Reset Operation
        • Figure - Figure 6-13: Reset Behavior Timing Diagram (Requires sync wrrst )
        • Heading3 - Writing an Empty Asynchronous FIFO (sync_mode = 1’b0)
        • Figure - Figure 6-14: Writing an Empty Asynchronous FIFO (sync_mode = 1’b0)
        • Heading3 - Writing an Empty Synchronous FIFO (sync_mode = 1’b1)
        • Figure - Figure 6-15: Writing an Empty Synchronous FIFO (sync_mode = 1’b1)
        • Heading3 - Writing to an Almost Full FIFO (en_wr_when_full = 1’b0)
        • Figure - Figure 6-16: Writing to an Almost Full FIFO (en_wr_when_full = 1’b0)
        • Heading3 - Writing to an Almost Full FIFO (en_wr_when_full = 1’b1)
        • Figure - Figure 6-17: Writing to an Almost Full FIFO (en_wr_when_full = 1’b1)
        • Heading3 - Reading from an Almost Empty FIFO (en_rd_when_empty = 1’b0, fwft = 1’b0)
        • Figure - Figure 6-18: Reading From an Almost Empty FIFO (en_rd_when_empty = 1’b0, fwft = 1’b0)
        • Heading3 - Reading from an Almost Empty FIFO (en_rd_when_empty = 1’b0, fwft = 1’b1)
        • Figure - Figure 6-19: Reading From an Almost Empty FIFO (en_rd_when_empty = 1’b0, fwft = 1’b1)
        • Heading3 - Reading from an Almost Empty FIFO (en_rd_when_empty = 1’b1)
        • Figure - Figure 6-20: Reading From an Almost Empty FIFO (en_rd_when_empty = 1’b1)
        • Figure - Figure 6-21: Writing and Reading a Mixed-Width FIFO
        • Heading3 - Limitations of Concurrent Read/Write Operations
    • Heading1 - BRAM80KECC
      • Heading2 - 80k-bit Simple Dual-Port Memory with Error Correction
        • Figure - Figure 6-22: Logic Symbol
        • Figure - Figure 6-23: BRAM80KECC Block Diagram
      • Heading2 - BRAM80KECC Pins
        • Table - Table 6-41: BRAM80KECC Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 6-42: BRAM80KECC Parameters
        • Heading3 - en_out_reg
        • Heading3 - reg_initval
        • Table - Table 6-43: Relationship of reg_initval bit positions to dout,doutp,doutpx
        • Heading3 - reg_srval
        • Table - Table 6-44: Relationship of reg_srval bit positions to dout,doutp,doutpx
        • Heading3 - reg_rstval
        • Heading3 - encoder_enable
        • Heading3 - decoder_enable
        • Heading3 - mem_init_file
        • Heading3 - initd_000 – initd_255
        • Heading3 - initp_0 – initp_31
        • Heading3 - initpx_0 – initpx_31
      • Heading2 - BRAM80KECC Modes of Operation
        • Table - Table 6-45: BRAM80KECC Modes of Operation
      • Heading2 - ECC Encode/Decode Operation Mode
      • Heading2 - ECC Encode-Only Operation Mode
      • Heading2 - ECC Decode-Only Operation Mode
        • Figure - Figure 6-24: ECC Write Operation Timing Diagram
        • Figure - Figure 6-25: ECC Read Operation Timing Diagram
        • Figure - Figure 6-26: ECC Read Operation Timing Diagram
    • Heading1 - BRAM80KECCFIFO
      • Heading2 - 80k-bit FIFO Memory with Error Correction
        • Figure - Figure 6-27: Logic Symbol
        • Figure - Figure 6-28: BRAM80KECCFIFO Block Diagram
        • Table - Table 6-46: BRAM80KECCFIFO Pin Description
      • Heading2 - Parameters
        • Table - Table 6-47: BRAM80KECCFIFO Parameters
    • Heading1 - LRAM640
      • Heading2 - 640-bit (64x10) Simple-Dual-Port Memory
        • Figure - Figure 6-29: Logic Symbol
        • Figure - Figure 6-30: LRAM640 Block Diagram
      • Heading2 - LRAM640 Pins
        • Table - Table 6-48: LRAM640 Pin Descriptions
      • Heading2 - Parameters
        • Table - Table 6-49: LRAM640 Parameters
        • Heading3 - write_clock_polarity
        • Heading3 - read_clock_polarity
        • Heading3 - reg_dout
        • Heading3 - reg_initval
        • Heading3 - reg_rstval
        • Heading3 - regce_priority
        • Heading3 - mem_init
        • Heading3 - mem_init_file
      • Heading2 - Simultaneous Memory Operations
      • Heading2 - LRAM640 Memory Initialization
    • Heading1 - LRAMFIFO
      • Heading2 - LRAM-Based 64-Word FIFO Memory
        • Figure - Figure 6-31: Logic Symbol
        • Figure - Figure 6-32: LRAMFIFO Block Diagram
        • Table - Table 6-50: LRAMFIFO Pin Description
      • Heading2 - Parameters
        • Table - Table 6-51: LRAMFIFO Parameters
        • Heading3 - width
        • Heading3 - depth
        • Heading3 - ptr_sync_mode
        • Heading3 - wrptr_sync_stages
        • Table - Table 6-52: Mapping wrptr_sync_stages Parameter Settings to Synchronization Stage Depth
        • Figure - Figure 6-33: Write Pointer Synchronizer Block Diagram
        • Heading3 - rdptr_sync_stages
        • Table - Table 6-53: Mapping rdptr_sync_stages Parameter Settings to Synchronization Stage Depth
        • Figure - Figure 6-34: Read Pointer Synchronizer Block Diagram
        • Heading3 - rst_sync_mode
        • Heading3 - wrrst_sync_stages
        • Table - Table 6-54: Mapping wrrst_sync_stages Parameter Settings to Synchronization Stage Depth
        • Figure - Figure 6-35: Write Pointer Reset Input Selection Block Diagram
        • Heading3 - rdrst_sync_stages
        • Table - Table 6-55: Mapping rdrst_sync_stages Parameter Settings to Synchronization Stage Depth
        • Figure - Figure 6-36: Read Pointer Reset Input Selection Block Diagram
        • Heading3 - afull_offset
        • Table - Table 6-56: Condition to Assert almost_full Flag based on afull_offset Parameter Assignment
        • Heading3 - aempty_offset
        • Table - Table 6-57: Condition to Assert almost_empty Flag based on aempty_offset Parameter Assignment
      • Heading2 - Status Flags
        • Heading3 - Empty Flag
        • Heading3 - Almost Empty Flag
        • Heading3 - Full Flag
        • Heading3 - Almost Full Flag
        • Heading3 - Write Error Flag
        • Heading3 - Read Error Flag
      • Heading2 - Flag Latency in Asynchronous Mode (ptr_sync_mode = 1’b0)
        • Table - Table 6-58: FIFO Pointers and Status Flag Clock Domain Assignments
        • Table - Table 6-59: Pointers Used for FIFO Flag Calculations (ptr_sync_mode = 1’b0)
        • Table - Table 6-60: Empty and Almost Empty Flag Latency in Terms of Read Clock Cycles(ptr_sync_mode =1’b0)
        • Table - Table 6-61: Full and Almost Full Flag Latency in Terms of Write Clock Cycles(ptr_sync_mode = 1’b0)
      • Heading2 - Flag Latency in Synchronous Mode (ptr_sync_mode = 1’b1)
      • Heading2 - FIFO Operational Modes
        • Heading3 - Asychronous FIFO Mode (ptr_sync_mode = 1’b0)
        • Heading3 - Synchronous FIFO Mode (ptr_sync_mode = 1’b1)
      • Heading2 - FIFO Operations
        • Heading3 - Asynchronous FIFO Mode Reset Operation
        • Figure - Figure 6-37: Asynchronous FIFO Mode Reset Timing Diagram
        • Heading3 - Writing an Empty Asynchronous FIFO (ptr_sync_mode = 1’b0)
        • Figure - Figure 6-38: Writing an Empty Asynchronous FIFO (ptr_sync_mode = 1’b0)
        • Heading3 - Writing an Empty Synchronous FIFO (ptr_sync_mode = 1’b1)
        • Figure - Figure 6-39: Writing an Empty Synchronous FIFO (ptr_sync_mode = 1’b1)
        • Heading3 - Writing to an Almost Full FIFO
        • Figure - Figure 6-40: Writing to an Almost Full FIFO
        • Heading3 - Reading from an Almost Empty FIFO
        • Figure - Figure 6-41: Reading From an Almost Empty FIFO
  • ChapterTitle - Chapter 7 – Multipliers
    • Heading1 - BMACC56
      • Heading2 - 28 x 28 Multiplier / Accumulator
        • Figure - Figure 7-1: Logic Symbol
        • Figure - Figure 7-2: BMACC56 Block Diagram
        • Table - Table 7-1: I/O Count
      • Heading2 - BMACC56 Pins
        • Table - Table 7-2: BMACC56 Pin Description
      • Heading2 - Parameters
        • Table - Table 7-3: BMACC56 Parameters
        • Heading3 - init_a
        • Heading3 - init_b
        • Heading3 - init_sub
        • Heading3 - init_cin
        • Heading3 - init_mask_adda
        • Heading3 - init_dout
        • Heading3 - init_cout
        • Heading3 - rst_value_a
        • Heading3 - rst_value_b
        • Heading3 - rst_value_sub
        • Heading3 - rst_value_cin
        • Heading3 - rst_value_mask_adda
        • Heading3 - rst_value_dout
        • Heading3 - rst_value_cout
        • Heading3 - regce_priority_a
        • Heading3 - regce_priority_b
        • Heading3 - regce_priority_sub
        • Heading3 - regce_priority_cin
        • Heading3 - regce_priority_dout
        • Heading3 - reg_a
        • Heading3 - reg_b
        • Heading3 - reg_addb
        • Heading3 - reg_mask_adda
        • Heading3 - reg_dout
        • Heading3 - reg_cout
        • Heading3 - sel_cascade_in
        • Heading3 - sel_cascade_out
        • Heading3 - sel_cin
        • Table - Table 7-4: Add/Sub Block Carry Input Assignment
        • Heading3 - sel_sub
        • Table - Table 7-5: Add/Sub Block Sub Input Assignment
        • Heading3 - mult_bypass
        • Heading3 - clock_edge
      • Heading2 - BMACC56 Verilog Instantiation Template
      • Heading2 - BMACC56 VHDL Instantiation Template
    • Heading1 - BMULT28X28
      • Heading2 - 28 ´ 28 Signed Multiplier
        • Figure - Figure 7-3: Logic Symbol
        • Table - Table 7-6: Pin Description
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
  • ChapterTitle - Chapter 8 – Special Functions
    • Heading1 - ACX_DESERIALIZE (Speedster22iHP Only)
      • Heading2 - 1:N Serial-to-Parallel Converter
        • Figure - Figure 8-1: Logic Symbol
        • Table - Table 8-1: Pin Description
        • Table - Table 8-2: Parameters
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
    • Heading1 - ACX_SERIALIZE (Speedster22iHP Only)
      • Heading2 - N:1 Parallel-to-Serial Converter
        • Figure - Figure 8-2: Logic Symbol
        • Table - Table 8-3: Pin Description
        • Table - Table 8-4: Parameters
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
  • ChapterTitle - Chapter 9 – PLL/DLL Clock Generators
    • Heading1 - ACX_CLKGEN
      • Heading2 - Phase-Locked Loop Clock Generator
        • Figure - Figure 9-1: ACX_CLKGEN Logic Symbol
      • Heading2 - ACX_CLKGEN Pins
        • Table - Table 9-1: Ports
      • Heading2 - Parameters
        • Table - Table 9-2: Parameters
        • Figure - Figure 9-2: ACX_CLKGEN Block Diagram
      • Heading2 - ACX_CLKGEN Components
        • Heading3 - Reference Divider
        • Heading3 - Voltage Controlled Oscillator (VCO)
        • Heading3 - Phase Rotator with Output Divider
        • Heading3 - Output Synthesizer
        • Heading3 - Phase Frequency Detector (PFD)
        • Heading3 - Feedback Divider
        • Heading3 - Clock Feedback Selection
        • Table - Table 9-3: Clock Feedback Selection
        • Heading3 - PLL Control
        • Heading3 - Serial Control Bus (SCB)
        • Figure - Figure 9-3: Serial Control Bus Read Operation
        • Figure - Figure 9-4: Serial Control Bus Write Operation
      • Heading2 - Control Status Registers (CSR) Register Description
        • Table - Table 9-4: Control Status Registers (CSR) Description
        • Heading3 - Verilog Instantiation Template
        • Heading3 - VHDL Instantiation Template
  • ChapterTitlePreface - Revision History