Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template, Verilog instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 29: Vhdl instantiation template
I/O Cells
IOPAD_D2
Speedster Macro Cell Library
PAGE 12
Verilog Instantiation Template
IOPAD_D2 #(.location(""),
.iostandard("LVCMOS18"),
.drive("16"),
.rstmode("async"),
.rstvalue("low"),
.slew("slow"),
.keepmode("none"),
.hysteresis("none"),
.open_drain("false"),
.pvt_comp("none"),
.termination("50"),
.odt("off"))
instance_name (.pad(user_pad), .dina(user_dina), .dinb(user_dinb),
.douta(user_douta), .doutb(user_doutb), .oe(user_oe),
.txdata_en(user_txdata_en), .rxdata_en(user_rxdata_en),
.txrstn(user_txrstn), .rxrstn(user_rxrstn), .oerstn(user_rxrstn),
.srstn(user_txsrstn), ..txclk(user_txclk), .rxclk(user_rxclk),
.oeclk(user_oeclk));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
IOPAD_D2_instance_name : IOPAD_D2
generic map (location => ““,
iostandard => “LVCMOS18”,
drive => "16",
rstmode => “async”,
rstvalue => “low”,
slew => “slow”,
keepmode => "none",
hysteresis => "none",
open_drain => "false",
pvt_comp => "none,
termination => "50",
odt => "off")
port map (pad => user_pad,
dina => user_dina,
dinb => user_dinb,
douta => user_douta,
doutb => user_doutb,
oe => user_oe,
txrstn => user_txrstn,
rxrstn => user_rxrstn,
oerstn => user_oerstn,
srstn => user_srstn,
txclk => user_txclk,
rxclk => user_rxclk,
oeclk => user_oeclk);