Achronix Speedster22i User Macro Guide - Manual (Page 54)

I/O Cells OPAD_DIFFD
Speedster Macro Cell Library www.achronix.com PAGE 37
OPAD_DIFFD
Registered Differential Output Pad with Asynchronous or Synchro-
nous Set/Reset
q
ce
d
rstn
q
ce
d
rstn
rstn
din
pad
oe
clk
data_en
OPAD_DIFFD
padn
Figure 1-19: OPAD_DIFFD Logic Symbol
OPAD_DIFFD is a registered differential output pad. The output and output enable registers
are clocked on the rising edge of the clock. The active‐high oe register is asynchronously
cleared upon a low on the rstn input. Driving rstn low performs an asynchronous initialization
of the output register if the rstmode parameter is set to async and performs a sychronous
initialization of the output register if the rstmode parameter is set to sync. The value initialized
into the output register is determined by the value of the rstvalue parameter.
Table 1-42: Ports
Name Type Description
pad Device output pad.
padn Device complement output pad.
din
Positive-edge based data input. Data is clocked into the output register
upon the rising edge of the clk input, and is driven to the pad if the oe
input was high before the rising edge of the clk input.
oe
Output Enable. The output enable register transitions upon the rising edge
of the clock. A low value on the rstn input performs an asynchronous clear to
disable the output . A high value on oe enables the output pad upon the next
rising edge of the clock. A low value on oe disables the pad upon the next ris-
ing edge of the clock and places the pad in high impedance mode.
data_en
Output Register Clock Enable. A high value on data_en enables the Out-
put Register and Output Enable Register to clock the din input to the out-
put at the next rising edge of the clock. A low value on data_en allows the
Output Register to retain its current value.
rstn
Output Register Asynchronous Reset. A low value on the rstn input per-
forms an asynchronous clear of the Output Enable Register to disable the
output. If the value of the rstmode parameter is “async”, a low value on the
rstn input performs an asynchronous initialization of the Output Register.
If the value of the rstmode parameter is “sync”, a low value on the rstn
input performs a synchronous initialization of the Output Register on the
next rising edge of the clock. The value initialized into the Output Register
is determined by the value of the rstvalue parameter.
clk Output Register / Output Enable Register Clock input.
output
output
input
input
input
input
input