Achronix Speedster22i User Macro Guide - Manual (Page 128)

Memories BRAM80K
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 111
.rstregb(user_rstregb),
.outregceb(user_outregceb),
.clkb(user_clkb),
.doutb(user_doutb),
.doutpb(user_doutpb),
.doutpxb(user_doutpxb));
BRAM80K VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
BRAM80K_instance_name : BRAM80K
generic map (
porta_read_width => 40,
porta_write_width => 40,
porta_write_mode => "write_first",
porta_clock_polarity => "rise",
porta_en_out_reg => 0,
porta_regce_priority => "rstreg",
porta_peval => 1,
porta_reg_rstval => 1,
porta_latch_rstval => 1,
porta_initval => X"0000000000",
porta_srval => X"0000000000",
portb_read_width => 40,
portb_write_width => 40,
portb_write_mode => "write_first",
portb_clock_polarity => "rise",
portb_en_out_reg => 0,
portb_regce_priority => "rstreg",
portb_peval => 1,
portb_reg_rstval => 1,
portb_latch_rstval => 1,
portb_initval => X"0000000000",
portb_srval => X"0000000000",
mem_init_file => "",
initd_000 => X"0000000000000000000000000000000000000000000000000000000000000000",
initd_001 => X"0000000000000000000000000000000000000000000000000000000000000000",
initd_002 => X"0000000000000000000000000000000000000000000000000000000000000000",
initd_003 => X"0000000000000000000000000000000000000000000000000000000000000000",
initd_004 => X"0000000000000000000000000000000000000000000000000000000000000000",
initd_005 => X"0000000000000000000000000000000000000000000000000000000000000000",
initd_006 => X"0000000000000000000000000000000000000000000000000000000000000000",