Table - table 2-29: function table, Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 84
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Registers
DFFNEP
Speedster22i Macro Cell Library
PAGE 68
Table 2-29: Function Table
Inputs
Output
pn
ce
d
ckn
q
Verilog Instantiation Template
DFFNEP #(.init(1’b1))
instance_name
(.q(user_out),
.d(user_din),
.pn(user_preset)
.ce(user_clock_enable),
.ckn(user_clock));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
DFFNEP_instance_name : DFFNEP
generic map ( init => ‘1’)
port map (q => user_out,
d => user_din,
pn => user_preset,
ce => user_clock_enable,
ckn => user_clock);
X
0
X
X
Hold
0
1
X
1
1
1
0
0
1
1
1
1
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