Chaptertitle - chapter 2 – registers, Heading1 - naming convention, Heading1 - dff – Achronix Speedster22i User Macro Guide User Manual

Page 65: Heading2 - positive clock edge d-type register, Figure - figure 2-1: logic symbol, Heading2 - pins, Table - table 2-1: pin descriptions, Chapter 2 – “registers, Chapter 2 – registers, Naming convention

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Speedster22i Macro Cell Library

Achronix Semiconductor Proprietary

PAGE 49

Chapter 2 – Registers

Naming Convention

These Macros are named based upon their characteristics and behavior. In each case, the name 
begins  with  DFF  for  D‐type  Flip  Flop.  In  addition  to  DFF  each  has  one  or  more  modifiers 
which indicates it’s unique properties. 

The modifiers are:

E ‐ Enable

N ‐ Negatively Clocked

R ‐ Reset (has priority over enable)

S ‐ Set (has priority over enable)

C ‐ Clear (enable has priority)

P ‐ Preset (enable has priority)

DFF

Positive Clock Edge D-Type Register

d

ck

DFF

q

Figure 2-1: Logic Symbol

DFF is a single D‐type register with data input (d) and clock (ck) inputs and data (q) output. 
The data output is set to the value on the data input upon the next rising edge of the clock.

Pins

Table 2-1: Pin Descriptions

Name

Type

Description

d

Data input.

ck

Positive-edge clock input.

q

Data output. The value present on the data input is transferred to the q out-
put upon the rising edge of the clock.

input

input

output

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