Achronix Speedster22i User Macro Guide - Manual (Page 153)

Memories BRAM80KFIFO
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 136
Flag Latency in Terms of Read Clock Cycles and Table 6‐38: Full and Almost Full Flag
Latency in Terms of Write Clock Cycles show the latency for the FIFO flag calculations.
Table 6-37: Empty and Almost Empty Flag Latency in Terms of Read Clock Cycles
FIFO Status Flag Read Clock Cycle Latency (rdclk cycles)
Flag Assertion Flag Deassertion
Standard Mode
(fwft = 1’0)
FWFT Mode
(fwft = 1’b1)
Standard Mode
(fwft = 1’0)
FWFT Mode
(fwft = 1’b1)
empty flag 0 0 3 4
almost empty flag 0 0 3 3
Table 6-38: Full and Almost Full Flag Latency in Terms of Write Clock Cycles
FIFO Status Flag Write Clock Cycle Latency (wrclk cycles)
Flag Assertion Flag Deassertion
Standard Mode
(fwft = 1’0)
FWFT Mode
(fwft = 1’b1)
Standard Mode
(fwft = 1’0)
FWFT Mode
(fwft = 1’b1)
full flag 0 0 3 3
almost full flag 0 0 3 3
Optional Output Register
An optional output register may be enabled at the output of the FIFO to improve the clock to
out timing when in single clock mode (sync_mode = 1’b1). Enabling the output register adds
an a additional cycle of latency to the output data for each read operation. It should be
considered as an optional pipeline stage at the data output of the FIFO. The timing of the
FIFO flags is not changed when the output register is enabled. The output register is enabled
by setting the en_out_reg parameter to 1’b1. The output register is shown in
Figure
6‐8: BRAM80KFIFO Block Diagram . The output register has independent clock enable
(outregce) and synchronous reset (rstreg) inputs. The output register may be configured to
have an active‐high or active‐low reset input as determined by the reg_rstval parameter.
When rstreg is asserted, the value of the reg_srval is placed on the output of the register at the
next active edge of the rdclk clock. The initial power‐up value of the output register is defined
by the reg_initval parameter. The regce_priority parameter value determines if the reset
operation is dependent on the outregce input.
Table 6‐39: Function Table for Optional
Output Register (Assumes active‐high rdclk, active‐high outregce, and active‐high rstreg)
shows the functions of the optional output register.
Table 6-39: Function Table for Optional Output Register (Assumes active-high rdclk, active-high
outregce, and active-high rstreg)
Operation regce_priority rstreg outregce rdclk dout
Hold X X X X dout_previous
Hold “rstreg” 0 0

dout_previous
Update
Output
“rstreg” 0 1

fifo_output
Reset
Output
“rstreg” 1 X

reg_srval
Hold “regce” X 0

dout_previous
Update
Output
“regce” 0 1

fifo_output