Achronix Speedster22i User Macro Guide - Manual (Page 109)

Memories BRAM80K
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 92
porta_read_width(portb_read_width)
The porta_read_width(portb_read_width) parameter sets the read width for Port A(B). The
read width may vary from the write port width, but it must be within the allowable
combinations defined in the
Memory Organization and Data Input / Output Pin
Assignments section.
porta_write_width(portb_write_width)
The porta_write_width(porta_write_width) parameter sets the write width for Port A(B). The
read width may vary from the write port width, but it must be within the allowable
combinations defined in the
Memory Organization and Data Input / Output Pin
Assignments section.
porta_write_mode(portb_write_mode)
The porta_write_mode(portb_write_mode) parameter is used to define the response of the
Port A(B) output to write operations. If porta_write_mode(portb_write_mode) is set to
“no_change”, douta(doutb) will remain unchanged during write operations. If
porta_write_mode(portb_write_mode) is set to “write_first”, the data present on the
dina(dinb) input during the write operation will appear on the output of Port A(B) if the
appropriate write enable bit, wea(web), is high. Note that the BRAM80K does not support a
‘read‐first’ or ‘read‐before‐write’ mode. If this behavior is detected by synthesis, a warning
will be issued in the synthesis log file and a register file will be synthesized. To implement a
more efficient mapping of a ‘read‐first’ memory, the user should update his code to use an
Achronix BRAM80K_READ_FIRST soft macro. Please refer to
Support for Read‐First (Read‐
Before‐Write) Memory Operations for a further explanation of read‐first memory support.
porta_clock_polarity(portb_clock_polarity)
The porta_clock_polarity(portb_clock_polarity) parameter is used to set the active edge of the
Port A(B) clock. A value of “rise” corresponds to an active rising edge assignment while “fall”
corresponds to an active falling edge assignment. The default value of the
porta_clock_polarity(portb_clock_polarity) is “rise”.
porta_peval(portb_peval)
The porta_peval(portb_peval) parameter defines the active level of the Port A(B) pea(peb) port
enable input. Assigning a value of 1’b0 to porta_peval(portb_peval) configures the Port A(B)
pea(peb) port enable input to be active low, while an assignment to 1’b1 sets an active‐high
level. The default value of the porta_peval(portb_peval) parameter is 1’b1.
porta_latch_rstval(portb_latch_rstval)
The porta_latch_rstval(portb_latch_rstval) parameter defines the active level of the Port A(B)
output latch reset input. Assigning a value of 1’b0 to porta_latch_rstval(portb_latch_rstval)
configures the Port A(B) output latch to have an active‐low synchronous reset, while assigning
a value of 1’b1 configures the Port A(B) output latch to have an active‐high synchronous reset.
The default value of porta_latch_rstval(portb_latch_rstval) is 1’b1.
porta_en_out_reg(portb_en_out_reg)
The porta_en_out_reg(portb_en_out_reg) parameter determines whether the Port A(B) output
register is enabled. A value of 1’b0 disables the output register and results in a read latency of
one cycle, while a value of 1’b1 enables the output register and results in a read latency of two
cycles. The default value of the porta_en_out_reg(portb_en_out_reg) parameter is 1’b0.