Achronix Speedster22i User Macro Guide - Manual (Page 75)

Registers DFFER
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 59
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
DFFER_instance_name : DFFER
generic map (
init => ‘0’,
sr_assertion => “unclocked”)
port map (q => user_out,
d => user_din,
rn => user_reset,
ce => user_clock_enable,
ck => user_clock);