Heading3 - verilog instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 220
PLL/DLL Clock Generators
ACX_CLKGEN
Speedster Macro Cell Library
PAGE 203
Verilog Instantiation Template
ACX_CLKGEN #
(
.clkdiv (6'h1),
.intfb (1'b0),
.phaseinc_sat (1'b0),
.clkmult (8'h0),
.synthmode (1'b0),
.frac_div_ctrl (16'h0),
.clkouten_mode (1'b0),
.pll_user_reset_en (1'b0),
.pll_user_outrst_en (1'b0),
.pll_user_csrrst_en (1'b0),
.bypass0 (1'b0),
.outdiv0 (6'h4),
.en_phase0 (1'b1),
.static_phase0 (3'h0),
.dyn_phase0 (1'b0),
.byp_clkdiv0 (1'b1),
.high_cnt0 (10'h0),
CSR_ADDR_ADC_DATA1
8’h1A
0
output Reserved
Reserved
1
output Reserved
Reserved
2
output Reserved
Reserved
3
output Reserved
Reserved
4
output Reserved
Reserved
5
output Reserved
Reserved
6
output Reserved
Reserved
7
output Reserved
Reserved
CSR_ADDR_ADC_DATA2
8’h1B
0
output Reserved
Reserved
1
output Reserved
Reserved
2
output Reserved
Reserved
3
output Reserved
Reserved
4
output Reserved
Reserved
5
output Reserved
Reserved
6
output Reserved
Reserved
7
output Reserved
Reserved
CSR_ADDR_USER_CONTROL
8’h1C
0
in/out
csr_enable =
1’b0
CSR Control bit 0: [0]=CSR disabled, PLL
controlled by parameters; [1]=: CSR regis-
ters control the PLL operation.
1
in/out
Reserved
Reserved
2
in/out
Reserved
Reserved
3
output 1’b0
Not used.
4
output 1’b0
5
output 1’b0
6
output 1’b0
7
output 1’b0
CSR NAME
Addr.
Bit
Type
Initial Value
Description