Achronix Speedster22i User Macro Guide - Manual (Page 155)

Memories BRAM80KFIFO
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 138
FIFO may be configured with or without the output register enabled. When the output
register is disabled, there is a single cycle of latency for the FIFO read operations, but it has a
longer clock to output delay of the output data. To reduce the clock to out delay of the
synchronous FIFO, the output register may be enabled (en_out_reg = 1’b1), but the FIFO data
output has an additional cycle of latency. The latency of the flags is not changed by the setting
of the en_out_reg parameter.
FIFO Operations
Basic Mode FIFO Reset Operation
Several options are available to the user with regard to resetting the FIFO. The Basic FIFO
reset allows the user to reset the FIFO without having a detailed knowledge of the FIFO
sycnchronization circuit, where the reset timing is not critical to the FIFO operation. For users
that require faster response time between the reset and normal FIFO operation, several
advanced options are available as detailed below in
Advanced Mode FIFO Reset Operation .
For basic FIFO Reset, the user should connect the user reset signal to both the wrrst and rdrst
input pins. To reset the FIFO, the user will assert the reset signal for a minimum of three clock
cycles of the slower clock cycle between the wrclk and rdclk. Asserting the reset signal clears
both the Write Pointer and Read Pointer, sets the empty and almost_empty flags, and clears
the full and almost_full flags. The user may then release the reset signal. The user should not
attempt to read or write the FIFO while the reset is asserted or before three cycles after the
deassertion of the reset signal. For Basic FIFO operation, the parameters associated with reset
should be left with their default settings as shown in
Table 6‐40: Parameter Settings
Required for Basic Mode FIFO Reset Operation .
Table 6-40: Parameter Settings Required for Basic Mode FIFO Reset Operation
Parameter Parameter Setting for Basic Mode FIFO Reset Operation
wrrst_input_mode 2’b11
wrrst_sync_stages 2’b00
rdrst_input_mode 2’b11
rdrst_sync_stages 2’b00