Achronix Speedster22i User Macro Guide - Manual (Page 169)

Memories BRAM80KECC
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 152
Figure 6-24: ECC Write Operation Timing Diagram
Figure 6-25: ECC Read Operation Timing Diagram
Figure 6-26: ECC Read Operation Timing Diagram
wrclk
wren
din[31:0]
dinpx[3:0] (Decode-Only)
dinp[3:0] (Decode-Only)
enc_parity[6:0]
dinp 0 dinp 1 dinp 2 dinp 3 dinp 4 dinp 5 dinp 6
wraddr[10:0] waddr 0 waddr 1 waddr 2 waddr 3 waddr 4 waddr 5 waddr 6
din 0 din 1 din 2 din 3 din 4 din 5 din 6
dinpx 0 dinpx 1 dinpx 2 dinpx 3 dinpx 4 dinpx dinpx 6
encpar 0 encpar 1 encpar 2 encpar 3 encpar 4 encpar 5 encpar 6
rdclk
rden
dout[31:0]
doutpx[3:0] (Encode-Only)
doutp[3:0] (Encode-Only)
rdaddr[10:0] raddr 0 raddr 1 raddr 2 raddr 3 raddr 4
dout 0 dout 1 dout 2 dout 3 dout 4
sbit_error
dbit_error
rdaddrecc[10:0]
doutpx 0 doutpx 1 doutpx 2 doutpx 3 doutpx 4
doutp 0 doutp 1 doutp 2 doutp 3 doutp 4
sbe 0 sbe 1 sbe 2 sbe 3 sbe 4
dout 0 dout 0 dout 1 dout 2 dout 3
radecc 0 radecc 1 radecc 2 radecc 3 radecc 4
dout 4